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AM3715 Using Fixed Supplies

AndMan
Intellectual 335 points
Other Parts Discussed in Thread: AM3715

In our application, we would like to provide power to the AM3715 without using a PMIC. As a result, there are a number of power related questions that have come about (below).

Supply Voltages

  • I'd like to limit the number of unique rail voltages to two; ~1.2V shared by vdd_core and vdd_mpu_iva and 1.8V for the remainder. Ultimately our use case would require switching between retention and the OPP100 modes. Looking at the rail voltages specified in the datasheet in sections 4.3.4 - 4.3.6, I am confused by the specified maximum values. For example, Table 4-18 indicates the valid OPP100 voltage range is 1.08 min, 1.2 V max. I understand the minimum value, but what drives the maximum value? Would 1.2V (+/- a few % for regulator tolerance) be an acceptable selection for this voltage for the operating modes we are planning to use?


Sequencing

  • With the supplies being implemented in the fashion described above, is there an opportunity to simplify the rail sequencing requirements in section 3.5 of the datasheet?
  • During shutdown, section 3.5.2 step 2 states "Stop all signals driven to its balls (sys_32k, sys_xtalin)". Does this truly mean ALL nets driving inputs on the AM3715 must be removed, or just sys_32k, sys_xtalin?
  • Figure 3.2 shows the sequencing of the system and 32kHz clocks. When using an xtal for the system clock (as opposed to an external oscillator), is this sequencing requirement handled internally by the 3715? Also, does the sys-32k input require that the enable on this signal be syncronous with the signal itself, or will it tolerate a small amount of glitching that an asynchronous buffer enable would cause?


Thanks - AM

  • 0
    TI__Genius 16690 points

    AndMan said:
    I understand the minimum value, but what drives the maximum value?

    The max and min voltage basically describes power supply tolerance. The power supply voltage should be 1.14V +/- 5 % for OPP100. Please also refer to this website.

    AndMan said:
    With the supplies being implemented in the fashion described above, is there an opportunity to simplify the rail sequencing requirements in section 3.5 of the datasheet?

    vdd_core and vdd_mpu_iva can be powered up by the same time and  possibly the same power supply depending on your use case.

    AndMan said:
    During shutdown, section 3.5.2 step 2 states "Stop all signals driven to its balls (sys_32k, sys_xtalin)". Does this truly mean ALL nets driving inputs on the AM3715 must be removed, or just sys_32k, sys_xtalin?

     just sys_32k, sys_xtalin

    AndMan said:
    Figure 3.2 shows the sequencing of the system and 32kHz clocks. When using an xtal for the system clock (as opposed to an external oscillator), is this sequencing requirement handled internally by the 3715? Also, does the sys-32k input require that the enable on this signal be syncronous with the signal itself, or will it tolerate a small amount of glitching that an asynchronous buffer enable would cause?

    32 kHz should be stabilized before system clock generated by internal oscillator and crystal becomes stable. 

    sys_nrespwron should be asserted until system clock becomes stable.