SK-AM62A-LP: Boot not working on AM62A3

Nathan De Souza

Part Number: SK-AM62A-LP
Other Parts Discussed in Thread: AM62A3, AM62A7

Hello,

I encountered some problems booting on SD card on my own board (similar to the SK-AM62A-LP) with a dual-core AM62A3.

The .wic file was made from SDK 11.01.05.07 with Yocto and the only file modified was the k3-am62a7.dtsi by deleting the lines related to two of the four CPUs. This file is properly working with the same board but with a quad-core AM62A7. However, with the dual-core AM62A3, it does not work at all (not even a single character in the console during boot).

Is deleting these lines sufficient to work, or do I need to modify other things for the AM62A32 ?

17 days ago

0 Suren Porwar 17 days ago

TI__Mastermind 36400 points

Hi Nathan,

Can you share the device tree file that you modified for supporting you better?

Best Regards

Suren

0 Suren Porwar 17 days ago in reply to Suren Porwar

TI__Mastermind 36400 points

Hi Nathan,

Also, have you followed the instructions provided in the below link to reduce the number of cores.

https://dev.ti.com/tirex/explore/node?a=7qm9DIS__LATEST&isTheia=false&node=A__AXjtetWgj.L6DlU8z-5kSg__AM62A-ACADEMY__WeZ9SsL__LATEST

Academy->Linux->Porting Linux to Custom Hardware -> Porting CPU section.

Best Regards

Suren

0 Nathan De Souza 14 days ago in reply to Suren Porwar

Prodigy 10 points

Hi Suren,

Yes, I have followed the instructions in the link but it still didn't work. Here is the k3-am62a7-sk.dts file I modified.

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * AM62A SK: https://www.ti.com/lit/zip/sprr459
 *
 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62a7.dtsi"

#include "k3-timesync-router.h"

/ {
	compatible = "ti,am62a7-sk", "ti,am62a7";
	model = "Texas Instruments AM62A7 SK";

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		serial2 = &main_uart0;
		serial3 = &main_uart1;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
		rtc0 = &wkup_rtc0;
		rtc1 = &tps659312;
		ethernet0 = &cpsw_port1;
		spi0 = &ospi0;
		usb0 = &usbss0;
		gpio0 = &main_gpio0;
		gpio1 = &main_gpio1;
	};

	chosen {
		stdout-path = "serial2:115200n8";
	};

	memory@80000000 {
		device_type = "memory";
		/* 2G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* global cma region */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x00 0x28000000>;
			alloc-ranges = <0x00 0xc0000000 0x00 0x28000000>;
			linux,cma-default;
		};

		c7x_0_dma_memory_region: c7x-dma-memory@99800000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x99800000 0x00 0x100000>;
			no-map;
		};

		c7x_0_memory_region: c7x-memory@99900000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x99900000 0x00 0x01f00000>;
			no-map;
		};

		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9b800000 0x00 0x100000>;
			no-map;
		};

		mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9b900000 0x00 0xf00000>;
			no-map;
		};

		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9c800000 0x00 0x100000>;
			no-map;
		};

		wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9c900000 0x00 0x1e00000>;
			no-map;
		};

		secure_tfa_ddr: tfa@9e780000 {
			reg = <0x00 0x9e780000 0x00 0x80000>;
			alignment = <0x1000>;
			no-map;
		};

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
			alignment = <0x1000>;
			no-map;
		};

		rtos_ipc_memory_region: ipc-memories@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x01000000>;
			no-map;
		};
	};

	opp-table {
		/* Requires VDD_CORE at 0v85 */
		opp-1400000000 {
			opp-hz = /bits/ 64 <1400000000>;
			opp-supported-hw = <0x01 0x0004>;
			clock-latency-ns = <6000000>;
		};
	};

	vmain_pd: regulator-0 {
		/* TPS25750 PD CONTROLLER OUTPUT */
		compatible = "regulator-fixed";
		regulator-name = "vmain_pd";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_5v0: regulator-1 {
		/* Output of TPS63070 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vmain_pd>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_3v3_main: regulator-2 {
		/* output of LM5141-Q1 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_main";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vmain_pd>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: regulator-3 {
		/* TPS22918DBVR */
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
	};

	vcc_3v3_sys: regulator-4 {
		/* output of TPS222965DSGT */
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_sys";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc_3v3_main>;
		regulator-always-on;
		regulator-boot-on;
	};

	vddshv_sdio: regulator-5 {
		compatible = "regulator-gpio";
		regulator-name = "vddshv_sdio";
		pinctrl-names = "default";
		pinctrl-0 = <&vddshv_sdio_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&ldo1>;
		gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};
};

&mcu_pmx0 {
	wkup_uart0_pins_default: wkup-uart0-default-pins {
		pinctrl-single,pins = <
			AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
			AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
			AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
			AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
		>;
	};
};

/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
	status = "reserved";
};

&main_pmx0 {
	main_uart0_pins_default: main-uart0-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
			AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
		>;
	};

	main_uart1_pins_default: main-uart1-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */
			AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */
			AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */
			AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
		>;
	};

	main_i2c0_pins_default: main-i2c0-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
			AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
		>;
	};

	main_i2c1_pins_default: main-i2c1-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
			AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
		>;
	};

	main_i2c2_pins_default: main-i2c2-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
			AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
		>;
	};

	main_mmc0_pins_default: main-mmc0-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
			AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
			AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
			AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
			AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
			AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
			AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
			AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
			AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
			AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
			AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
		>;
	};

	main_mmc1_pins_default: main-mmc1-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
			AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
			AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
			AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
			AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
			AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
			AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
		>;
	};

	main_usb0_pins_default: main-usb0-pins-default {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x0254, PIN_INPUT, 0) /* (C20) USB0_DRVVBUS */
			AM62AX_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) SPI0_D0.GPIO1_18 */
		>;
	};

	main_usb1_pins_default: main-usb1-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
		>;
	};

	main_mdio1_pins_default: main-mdio1-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
			AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
		>;
	};

	main_rgmii1_pins_default: main-rgmii1-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
			AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
			AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
			AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
			AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
			AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
			AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
			AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
			AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
			AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
			AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
			AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
		>;
	};

	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */
		>;
	};

	vddshv_sdio_pins_default: vddshv-sdio-default-pins {
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */
		>;
	};

	ospi0_pins_default: ospi0-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62AX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */
			AM62AX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */
			AM62AX_IOPAD(0x000c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */
			AM62AX_IOPAD(0x0010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */
			AM62AX_IOPAD(0x0014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */
			AM62AX_IOPAD(0x0018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */
			AM62AX_IOPAD(0x001c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */
			AM62AX_IOPAD(0x0020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */
			AM62AX_IOPAD(0x0024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */
			AM62AX_IOPAD(0x0028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
			AM62AX_IOPAD(0x0008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */
		>;
	};
};

&mcu_pmx0 {
	status = "okay";

	pmic_irq_pins_default: pmic-irq-default-pins {
		pinctrl-single,pins = <
			AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */
		>;
	};
};

&mcu_gpio0 {
	status = "okay";
};

&main_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;
	tps659312: pmic@48 {
		compatible = "ti,tps6593-q1";
		reg = <0x48>;
		ti,primary-pmic;
		system-power-controller;

		gpio-controller;
		#gpio-cells = <2>;

		pinctrl-names = "default";
		pinctrl-0 = <&pmic_irq_pins_default>;
		interrupt-parent = <&mcu_gpio0>;
		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;

		buck123-supply = <&vcc_3v3_sys>;
		buck4-supply = <&vcc_3v3_sys>;
		buck5-supply = <&vcc_3v3_sys>;
		ldo1-supply = <&vcc_3v3_sys>;
		ldo2-supply = <&vcc_3v3_sys>;
		ldo3-supply = <&buck5>;
		ldo4-supply = <&vcc_3v3_sys>;

		regulators {
			buck123: buck123 {
				regulator-name = "vcc_core";
				regulator-min-microvolt = <715000>;
				regulator-max-microvolt = <895000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4: buck4 {
				regulator-name = "vcc_1v1";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5: buck5 {
				regulator-name = "vcc_1v8_sys";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1: ldo1 {
				regulator-name = "vddshv5_sdio";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2: ldo2 {
				regulator-name = "vpp_1v8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3: ldo3 {
				regulator-name = "vcc_0v85";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4: ldo4 {
				regulator-name = "vdda_1v8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&main_i2c1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <100000>;

	exp1: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio1>;
		interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;

		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
				   "BT_EN_SOC", "MMC1_SD_EN",
				   "VPP_EN", "EXP_PS_3V3_En",
				   "EXP_PS_5V0_En", "EXP_HAT_DETECT",
				   "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
				   "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC",
				   "GPIO_HDMI_RSTn", "CSI_GPIO0",
				   "CSI_GPIO1", "WLAN_ALERTn",
				   "HDMI_INTn", "TEST_GPIO2",
				   "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
				   "MCASP1_FET_SEL", "UART1_FET_SEL",
				   "PD_I2C_IRQ", "IO_EXP_TEST_LED";
	};
	exp2: gpio@23 {
		compatible = "ti,tca6424";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;

		gpio-line-names = "", "",
				  "", "",
				  "", "",
				  "", "",
				  "WL_LT_EN", "CSI_RSTz",
				  "", "",
				  "", "",
				  "", "",
				  "SPI0_FET_SEL", "SPI0_FET_OE",
				  "RGMII2_BRD_CONN_DET", "CSI_SEL2",
				  "CSI_EN", "AUTO_100M_1000M_CONFIG",
				  "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST";
	};
};

&main_i2c2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c2_pins_default>;
	clock-frequency = <400000>;
};

&sdhci0 {
	/* eMMC */
	bootph-all;
	status = "okay";
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc0_pins_default>;
	disable-wp;
};

&sdhci1 {
	/* SD/MMC */
	status = "okay";
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vddshv_sdio>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	disable-wp;
};

&main_gpio0 {
	status = "okay";
};

&main_gpio1 {
	status = "okay";
};

&main_gpio_intr {
	status = "okay";
};

&main_uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	interrupts-extended = <&gic500 GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
			<&main_pmx0 0x1c8>; /* (D14) UART0_RXD PADCONFIG114 */
	interrupt-names = "irq", "wakeup";
};

/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart1_pins_default>;
	status = "reserved";
};

/* main_timer2 is used by C7x DSP */
&main_timer2 {
	status = "reserved";
};

&usbss0 {
	status = "okay";
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "peripheral";
	pinctrl-names = "default";
	pinctrl-0 = <&main_usb0_pins_default>;
};

&usbss1 {
	status = "okay";
};

&usb1 {
	dr_mode = "host";
	pinctrl-names = "default";
	pinctrl-0 = <&main_usb1_pins_default>;
};

&cpsw3g {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_rgmii1_pins_default>;

	cpts@3d000 {
		/* MAP HW3_TS_PUSH to GENF1 */
		ti,pps = <2 1>;
	};
};

&cpsw_port1 {
	status = "okay";
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy0>;
};

&cpsw_port2 {
	status = "disabled";
};

&cpsw3g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mdio1_pins_default>;

	cpsw3g_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&fss {
	status = "okay";
};

&ospi0 {
	status = "disabled";
	bootph-all;
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;

	flash@0{
		compatible = "spi-nand";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;
		cdns,phy-mode;
		bootph-all;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			bootph-all;

			partition@0 {
				label = "ospi_nand.tiboot3";
				reg = <0x0 0x80000>;
			};

			partition@80000 {
				label = "ospi_nand.tispl";
				reg = <0x80000 0x200000>;
			};

			partition@280000 {
				label = "ospi_nand.u-boot";
				reg = <0x280000 0x400000>;
			};

			partition@680000 {
				label = "ospi_nand.env";
				reg = <0x680000 0x40000>;
			};

			partition@6c0000 {
				label = "ospi_nand.env.backup";
				reg = <0x6c0000 0x40000>;
			};

			partition@2000000 {
				label = "ospi_nand.rootfs";
				reg = <0x2000000 0x5fc0000>;
			};

			partition@7fc0000 {
				label = "ospi_nand.phypattern";
				reg = <0x7fc0000 0x40000>;
				bootph-all;
			};
		};
	};
};

&mailbox0_cluster0 {
	ti,mbox-num-fifos = <2>;
	mbox_r5_0: mbox-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&mailbox0_cluster1 {
	ti,mbox-num-fifos = <2>;
	mbox_c7x_0: mbox-c7x-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&mailbox0_cluster2 {
	ti,mbox-num-fifos = <2>;
	mbox_mcu_r5_0: mbox-mcu-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&wkup_r5fss0 {
	status = "okay";
};

&wkup_r5fss0_core0 {
	mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>;
	memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
			<&wkup_r5fss0_core0_memory_region>;
};

&mcu_r5fss0 {
	status = "okay";
};

&mcu_r5fss0_core0 {
	mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>;
	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
			<&mcu_r5fss0_core0_memory_region>;
};

&c7x_0 {
	mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>;
	memory-region = <&c7x_0_dma_memory_region>,
			<&c7x_0_memory_region>;
	status = "okay";
};

&main_rti1 {
        status = "reserved";
};

&main_rti2 {
        status = "disabled";
};

&main_rti3 {
        status = "disabled";
};

/* main_rti4 is used by C7x DSP */
&main_rti4 {
	status = "reserved";
};

&timesync_router {
	/* Use Time Sync Router to map GENF1 input to HW3_TS_PUSH output */
	mux-reg-masks-state = <
		/* pps [cpsw cpts genf1] in17 -> out12 [cpsw cpts hw3_push] */
		K3_TS_OFFSET(12, 0x0001ffff, 17)
		>;
	status = "okay";
};

cpus {
                /delete-node/ cpu@2;
                /delete-node/ cpu@3;
};

&cluster0 {
                /delete-node/ core2;
                /delete-node/ core3;
};

And here is the k3-am62a7.dtsi file:

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for AM62A3 SoC family in Dual core configuration
 *
 * TRM: https://www.ti.com/lit/zip/spruj16
 *
 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-am62a.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0: cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			reg = <0x000>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
			operating-points-v2 = <&a53_opp_table>;
			clocks = <&k3_clks 135 0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
			operating-points-v2 = <&a53_opp_table>;
			clocks = <&k3_clks 136 0>;
		};
	};

	a53_opp_table: opp-table {
		compatible = "operating-points-v2-ti-cpu";
		opp-shared;
		syscon = <&opp_efuse_table>;

		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			opp-supported-hw = <0x01 0x0007>;
			clock-latency-ns = <6000000>;
		};

		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-supported-hw = <0x01 0x0007>;
			clock-latency-ns = <6000000>;
		};

		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-supported-hw = <0x01 0x0007>;
			clock-latency-ns = <6000000>;
		};

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-supported-hw = <0x01 0x0007>;
			clock-latency-ns = <6000000>;
		};

		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-supported-hw = <0x01 0x0006>;
			clock-latency-ns = <6000000>;
		};

		opp-1250000000 {
			opp-hz = /bits/ 64 <1250000000>;
			opp-supported-hw = <0x01 0x0004>;
			clock-latency-ns = <6000000>;
			opp-suspend;
		};
	};

	L2_0: l2-cache0 {
		compatible = "cache";
		cache-unified;
		cache-level = <2>;
		cache-size = <0x80000>;
		cache-line-size = <64>;
		cache-sets = <512>;
	};
};

Best regards,

Nathan

0 Suren Porwar 11 days ago in reply to Nathan De Souza

TI__Mastermind 36400 points

Nathan,

As you mentioned you are not seeing any UART console logs, can you switch to UART boot mode to see the console UART print any message? Looks like a board issue.

Best Regards

Suren

0 Nathan De Souza 9 days ago

Prodigy 10 points

Hi Suren,

Yes in UART Boot mode, I can see a message which is :

02000000011a0000616d3632610000000000000048534653000800000008000002a6000000000000cb39ee39c52d0469806636ff350520fcf7065cbec5cdddfea08863506c2be9f2242ff3207f919c2edcff407261f0908459139f3c153770f3024c4eae43a71151ad0bc40b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086eb864b363eaf14a7dba416e75f460ba68e08c5137c0859f6ad053e10ff2e6eCC

Best regards,

Nathan

0 Suren Porwar 9 days ago in reply to Nathan De Souza

TI__Mastermind 36400 points

Hi Nathan,

I discussed this internally and what I found was, the default wic Image should boot on AM62A3 except for few warnings that there are no 4 cores available.

Can you boot your AM62A3 board with our default image and share the log.

Also appreciate if you could provide the device tree blob that got generated with the device tree changes. It would help if you could attach both files.

Best Regards

Suren

0 Nathan De Souza 8 days ago in reply to Suren Porwar

Prodigy 10 points

Hi,

I tried with the default wic image but it is still not showing a thing.

Here is the device tree blob: am62a3.dtb.txt

Best regards,

Nathan

0 Suren Porwar 8 days ago in reply to Nathan De Souza

TI__Mastermind 36400 points

Hi Nathan,

Can you check the sysboot pin setting, to see if it matches the way that the sdcard is partitioned/programmed.
Also read the DEVSTAT register (0x43000030) via JTAG for the bootmode latched.

Best Regards

Suren

Processors

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SK-AM62A-LP: Boot not working on AM62A3