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Link training for an end point

Is it possible to initiate link training in an end point? It looks like it according to sprug6a. However after running the PCIE_example project for the TMDXEVM6678L and I display memory at location 0x21800004 it displays 0x00000006 instead of 0x00000007. Can you explain why this would be the case .

We are trying to creat a link between a PEX 8617 switch and the EVM card. The evm is not going past the link training check.

  • Additional Info:

    LTSSM state returns DEtect_QUIET or PRE_DETECT QUIET

  • Mark,

    May I ask if the PCIe_example project you are referring to is the one in the PDK package as follows please?

    "pdk_C6678_1_0_0_17\packages\ti\drv\pcie\example\sample"

    If so, is it being stuck at "pcieWaitLinkUp(handle);" or anywhere else please?

    And could you check if there is any difference by setting 1 to bit 0 (LTSSM_EN) in Command Status Register (0x21800004) manually and continue checking if the link is up (bits[4:0] in DEBUG0(0x21801728) = 0x11)? 

    On the PCIe switch side, could you check if any register needs to be setup for link up and all the configurations are setup correctly for link training please?

    Sincerely,

    Steven

  • Thanks Steven,

    Yes, I am running that example project.

    Yes, it is stuck in pcieWaitLinkUp.

    There is no difference between setting 1 to bit 0 (LTSSM_EN) in Command Status Register (0x21800004) manually.  I read back a 0x6 from the lower 4 bits.

    We also see activity on both sides of the capacitor on the the input to the DSP, but none on the output from the DSP for both  lanes.

    I Believe the switch is set up correctly and I have posted on the PEX website this same request but as of yet have not received and answer.

    Thanks,

    Mark

     

  • Some new info, the DSP PCIe is now stuck in LTSSM state 0x02 POLL_ACTIVE. We are going to try and remove one of the 0.1 uf caps. There are two in line on every signal path.

  • After correcting some Hardware connections with a new interface board the link is now up>

  • I am seeing similar type results.   The EVM (both a 6678 and 6657) are not generating any output of the TX pins.  I am also seeing the link state machine always  at DETECT.

    My setup is as follows:

    EVM with an adapter card that handles PCIe 1X and 2X boards.

    Additional REFCLK generation on board

    Running sample program in either RC or EP.   I get no errors and it indicates that everything is good up until it is waiting for the link to connect.

    Reading over the specfication, when the c66 is put into link training mode, I would expect to see data being transmitted out of the port.   I am seeing nothing.  I have checked both sides of the cap as well as disconnecting the target board.    Should I expect to see data?

    Paul

  • Paul,

    In the "DETECT" state, the device detects the presence or absence of a device connected at the far end of the link. The transmitter starts at a stable DC common mode voltage on all lanes. The transmitter then drives a DC common mode voltage other than the one currently presented. A receiver is detected based on the rate at which the D+ and D- lines charge to the new voltage. 

    At design time, the device is designed with knowledge of the charge time to change the voltage (based on the assumed line impedance and transmitter impedance without receiver termination). With a receiver attached at the other end, the charge time will be longer than if there is no connected receiver.

    In your setup, the C66x device may not be able to detect the other peer over the link and they are stuck in this state. I do not think you will see any data transaction in "DETECT" state (link training pattern will be observed in later states, such as Polling and Configuration states). 

    May I ask how to connect those two EVMs together please? Are you plugging those two into the same PCIe backplane?

    Or do you have the dual EVM breakout card and plug them into the card for the connection please?

    It looks like Mark was seeing the similar issue before but he resolved the issue by correcting some hardware connects with a new interface board.

    Mark,

    Could you please share what changes you have made in the hardware to get the link up please? Thanks.

  • We have a custom AMC to PCIe adapter card.    We had to do one since I could not find a readily availble solution when I was initially working on the project.

    What I need is the ability to connect a 66x via AMC to a FPGA evaluation card using a PCIe edge finger.    If you have a solution that has been testing, it would be helpful.

     

    Paul

     

  • One thing that Mark did discuss is the the presense of double capacitors.   How much of an effect do you think that might have on the detection circuit?

  • For our interface board we originally laid out the AMC connections backwards, or in other words we needed to creat a new inerface board to reroute the signal back to where they should have been. We also did elliminate the second capacitor in the path by replacing with zero ohm resistor. This may not hlep for your problem.

  • Mark,

    Thanks for the feedback.  I think that I was misinterpreting the detect phase.   My guess is that I will figure it out quickly.

     

    Paul

     

  • Hi Mark,
    What changes you made in the board or daughter card?

    Regards