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uPP Transmission Issue

Shino Samuel
Intellectual 990 points

Hi

I am currently working on a developed driver code to debug the problem with transmit/receive through DMA . The interface is between  OMAP- L138 processor & Vertex 6 FPGA and the code will configure uPP for duplex 2 mode. I will list out the issues for clarification;

1. Primary issue on uPP configuration: Driver Code will enable  WAIT signal for transmission and kept ENABLE & START signal in disable state. For receiver, the code will  configure ENABLE and START signal in enable state and WAIT in disable state. Now i checked the code with DLB and it works perfectly with EOWI/EOWQ /EOLI/EOLQ interrupt & data transfer. But in the case of actual trx (without DLB) with FPGA the EOLI is the only interrupt i got . Why this happen ? And i want the actual working configuration of START, ENABLE & WAIT signals for Trx and Rx . I also tried configurations with table 5 in uPP document. In all cases START bit is verified correctly by a scope but enable signal is missing.

2.     I also found the ENABLE bit at high logic state. so i just send the board back to hardware designers to provide a pull down through  4.7k resistor. Is it feasible? i checked all hardware lines with clock generated from FPGA. But from processor the Lines are not driving with the driver code.

3. since the line is at active high logic shall i try with inverted polarity???

4. I kept DMA descriptor register values as

Line Count: 1 (0x1)

Byte Count: 4096 (0x100 0x0)

and 64 byte DMA read/write.

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

I just invite attention from  any  uPP experts to solve my frozen situvation

Thank you. 

  • 0
    TI__Expert 8890 points

    Shino,

    Seeing an EOLI event but no EOWI event is strange, especially if the transfer consists of only one line, but it could indicate that there is some basic signal problem in your uPP-to-FPGA system.  The ENABLE signal should be driven by the uPP transmitter.  In duplex mode, this means that the uPP peripheral should drive one ENABLE pin, and the FPGA should drive the other ENABLE pin.

    For the uPP transmit channel, it should not be necessary to use a pull-down resistor on the ENABLE line.  If that line is floating high after the uPP module and pinmux have been setup, that could mean your FPGA is driving it high.  Is anything else connected to the ENABLE line besides the uPP and FPGA pins?

    For the uPP receive channel, the reverse should be true.  The uPP peripheral will not drive ENABLE in receive mode, so the line should always reflect the value being driven by the FPGA.

    One possible source of confusion is that the original EVM schematics labeled the uPP pins as belonging to "channel 0" or "channel 1".  Contrary to what you might expect, channel 0 actually corresponds to channel B, and channel 1 corresponds to channel A.  If you used the EVM schematics as a reference when designing your own board, you may be mixed up on which channel is transmitting and which is receiving.  You can fix this by switching your software to use the other duplex mode; there should be no need to redo the entire board.

    Hope this helps. Let me know if you have additional questions about uPP.