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TDA4VH-Q1: uboot boot error

an jianjun
Prodigy 20 points

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: SYSCONFIG, TDA4VH

dump.zip 

When performing powercycle, I occasionally found that the startup got stuck in U-Boot, and the data in norflash had been tampered with. Through the debugger, it was discovered that when U-Boot started, an error A occurred fi rst, and then the error handling would enter do_sync. There is a bug in do_sync This will trigger a series of nested errors. During this bunch of nesting, the SP pointer points to the mapping space of norflash, modifying the data of Norflash.

 

In the attachment, we have fixed do_sync, added some crash log records, and re-reproduced the scene of error A. Now, I would like to take A look at why error A occurred

  • 0
    TI__Guru**** 171090 points

    Hi,

    I could not understand all the information in the attached zip file. Can you please share the exact error in U-Boot that you are seeing?

    - Keerthy

  • 0
    Prodigy 20 points

    The phenomenon is that the program gets stuck as soon as it reaches U-Boot. The serial port of U-Boot does not print out any log. We connect to the debugger and obtain the data of DDR and registers. The content in the zip file is as follows:

    1.80470000-80480000. Bin

    2.80800000-80970000. Bin

    These two are the dump data corresponding to the DDR address

    3.reg.txt- Register values at the scene of the incident

    4.u-boot- The elf file of U-boot, which contains a symbol table

    5.uboot_early_abort_cr_122077956.md , uboot_early_abort_patch.md

    These two are our own fixes to do_sync and the code for saving the added registers to memory

    6.uboot_early_abort_dump_analysis.md

    This is some analysis of the above-mentioned accident scene by ai

  • 0 in reply to Keerthy J
    Prodigy 20 points

    ddr_par.zipIt was generated using the excel tool SPRACU8B_jacinto7_DDRS_RegConfigTool, whose version number is 23rd,2023, 0.10.0 this is our ddr parameter，

  • 0 in reply to an jianjun
    Prodigy 20 points

    the ddr_par.zip is our ddr parameter，It was generated using the excel tool SPRACU8B_jacinto7_DDRS_RegConfigTool, whose version number is 23rd,2023, 0.10.0 ， we just change the chip selects/ranks from 2 to 1，and multi DDRSS interleave memory size from 32GB to 16GB

  • 0 in reply to an jianjun
    Prodigy 160 points

    Hi,

    soc-LP4-sch.pdf

    attachment is LPDDR4 schematic.

    thanks

  • 0 in reply to gavin zhang
    TI__Guru**** 171090 points

    Hello,

    If you are suspecting DDR at least some of the R5 SPL logs should be up and DDR could fail after that - Can you share the working and non working boot logs?

    - Keerthy

  • 0 in reply to Keerthy J
    Prodigy 20 points

    Hello, could you please first help us analyze the fault site? The complete ddr and registers of the fault site are in the attachment. Then we can discuss whether it is a ddr issue

  • 0 in reply to an jianjun
    TI__Guru**** 171090 points

    Hi,

    This is not really helping me in any ways.

    Boot flow from TI Linux SDK:

    R5 SPL --> A72 ATF --> A72 SPL --> A72 U-boot --> A72 Linux/HLOS

    When the issue happens can you confirm you have reached the A72 U-Boot phase when you say U-Boot fails?
    If yes then share the boot logs till U-Boot.

    an jianjun said:
    could you please first help us analyze the fault site

    I am not sure what you mean by fault site.

    - Keerthy

  • 0 in reply to Keerthy J
    TI__Expert 6965 points

    Hi jianjun:

    I has compared your hardware used  MT53E1G32D2FW-046 AAT:C with EVM board used MT53E2G32D4DE-046. They are same die but 1G32D2 just has 1 Rank and EVM board 8GB 2G32D4 has 2 Rank.

    Below are using sysconfig latest 0.12 version input 1G32D2 generate parameter. Because the hardware PCB and impedance we do not know, the IO drive strength at TDA4VH and LPDDR4 side i do not change it. You can contact with your hardware experts double confirm those drive strength value. the excel tools is 0.10 version and 0.12 has enable DBI, optimize command bus training. 

    Suggest you use new tools generate DTSI file try it at your hardware.

    Best Regards!

    Han Tao

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0383.k3_2D00_j784s4_2D00_ddr_2D00_evm_2D00_lp4.dtsihttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0383.settings_5F00_info.syscfghttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/7635.untitled.syscfg

  • 0 in reply to Tao Han
    TI__Expert 6965 points

    Hi jianjun:

    At TDA4VH EVM board, i use 11.02.00.04 LInux release make the SD card. just copy boot partition file to SD card and keep rootfs partition is blank.

    I power on 10 second and power off 10 second at TDA4VH EVM board, run >3500 circle do not find LPDDR4 initial failure problem.

    Below is the log at TDA4VH uart output.you can search those ERROR/ k3_lpddr4_start: FAIL/lpddr4 in this log.

    Maybe your production board test, when you connect USB to UART IC at power on/off test. Those IC will leakage >0.3V voltage to TDA4VH and this kind of situation will trigger abnormal because TDA4VH need all IO voltage below to 0.3V at power off mode. i has capture those datasheet page 139 explain about it.

    Could you please confirm your side reproduce LPDDR4 initial failure test method at your side?

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/TDA4VHpoweronoff.7z

    Best Regards!

    Han Tao

  • 0 in reply to Tao Han
    TI__Mastermind 44790 points

    Hi,

    A few existing TI requests in this ticket that are not clear if they have been completed:

    Keerthy J said:
    If you are suspecting DDR at least some of the R5 SPL logs should be up and DDR could fail after that - Can you share the working and non working boot logs?

    Tao Han said:

    the excel tools is 0.10 version and 0.12 has enable DBI, optimize command bus training. 

    Suggest you use new tools generate DTSI file try it at your hardware.

    Can you please help provide an update on these requests?

    Thanks,
    Kevin