• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 98 subscribers
  • Views 1367 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Can C6678 be booted up directly from SPI Nor Flash ?

Nuoxi Lin
Intellectual 650 points
Other Parts Discussed in Thread: TMS320C6678

Hi all,

    I learned from a earlier post that It is poossible to boot C6678 directly from SPI Nor Flash, without the participation of I2C. But another post holds the view that FPGA is

programmed to force  the DSP boots from the I2C regardless of the boot strapping ,then it re-enters the bootrom and boots using the mode selected.This is due to the

 PLL fix.

    Now I am very confused with the following issues:

    1. Can C6678 be booted up directly from SPI Nor Flash,without the participation of I2C ?

    2.Is it necessary to program IBL and IBL configuration on I2C EEPROM at bus address 0x51 when I test  SPI boot mode on TMDXEVM6678L Rev0.2 ?

    Thanks in advance.

    Nuoxi Lin.

 

 

 

  • 0
    TI__Guru* 84110 points

    Nuoxi Lin,

    With the silicon revision 1.0, the PLL fix is required. On the EVM, this is implemented using an FPGA and I2C EEPROM 0x51 to allow you to have as much flexibility as possible with your EVM boot selection. When the PLL problem is fixed in the next revision of the silicon, this I2C PLL Fix will not be required.

    Please review the errata document to understand the conditions of the PLL locking problem and the workaround. This is Advisory 8.

    The errata specifies a workaround option for "no-boot, SPI and I2C boot modes", so you could do the same thing with a SPI Flash instead of I2C EEPROM.

    Nuoxi Lin said:

    1. Can C6678 be booted up directly from SPI Nor Flash,without the participation of I2C ?

    Yes, this can be done with the C6678. But this is not how the EVM is implemented. You could do this on your own board, but for the EVM we chose to use the FPGA to transparently override the boot mode to I2C for the PLL Fix.

    Nuoxi Lin said:

    2. Is it necessary to program IBL and IBL configuration on I2C EEPROM at bus address 0x51 when I test  SPI boot mode on TMDXEVM6678L Rev0.2 ?

    I do not know the EVM revision numbers so there could be updates that I do not know about. Because the FPGA overrides the boot mode, yes you must leave the IBL in the I2C EEPROM at address 0x51. After applying the PLL Fix, the IBL will read the DIP switches and will start the boot process again using the boot mode you select with the DIP switches.

    The IBL should already be programmed into the I2C correctly. All you should do is set the DIP switches to SPI boot mode and you will be able to test your SPI boot mode.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

  • 0 in reply to RandyP
    Intellectual 650 points

    Sorry for the delay. Your explanation is very detailed.  Thank you very much.

    Nuoxi

  • 0 in reply to RandyP
    Intellectual 650 points

    Hi RandyP,

        How to get the silicon revision number of C6678 DSP on my board?  I know from the  datasheet that   the silicon revision number  can be get  by reading  the value of

    Corepac Revision ID Register(MM_REVID), located at 0x01812000.  The value of MM_REVID is 0x0008 0000. But I still can't make out the revision number of C6678 DSP on

    myboard through this value.

        There sre some identifiers on the surface of the DSP on my board. They are:

        TMX320C6678CYP

       YB10 —17ZCSE9

        2010 TI  2  G1

    My purpose is to make sure if  PLL fix shoud be considered on my board based on C6678.

    Thanks in advance.

    Nuoxi

     

  • 0 in reply to Nuoxi Lin
    TI__Guru* 84110 points

    Nuoxi,

    The datasheet has a section on "device nomenclature" and the errata document has a section on "package symbolization". These tell you how to read the device markings on the top of the package.

    Please be aware that the TMX prefix is explained in the datasheet as are being an experimental device and not a production-qualified device. The TMS prefix indicates that the device has been through full TI qualification processes for our quality assurances.

    In addition, the errata document has information on the contents of the ID registers. This information is in that same section as the package markings.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 650 points

    RandyP,

        Thank you very much for your reply.  I have found the Information according to your instruction.

    Best wishes.

    Nuoxi 

  • 0 in reply to RandyP
    Intellectual 650 points

    Hi RandyP,

        I have managed to implement SPI boot on  EVM. Now I am trying to do this on my own board based on C6678. But I always fail.And I am confused with some questions.

        When testing SPI boot on EVM ,the input reference clock frequency is 100MHZ. Boot parameter table is as follows:

        length         80

       checksum     0

        boot mode      50

        port num      0

        swpllcfg_msw   0

        swpllcfg_lsw      0

        options       1

        addrwidth           24

        npins              4

        csel          0

        mode    0

        c2tdelay     0

        CPU Freq Mhz     800

        bus FreqMhz    0

         bus Freqkhz     500

        When testing SPI boot on my own board,the input reference clock frequency is 50MHZ and core frequency is 1000Mhz.  .  I think the parameter table should be the same as   EVM.  So I also used the boot parameter table above.   But it can't boot up. Here are my questions.

    1. Are there any differences between booting EVM and my own board with respect to boot parameter table?

        What should be considered to set bus FreqMhz  and bus Freqkhz?     The address width should be alwlays set to 24 bits,right?

    2. Since  the silicon revision number of my board is 1.0, I have to consider the PLL fix. I used a  function named  Init_PLL(), in which the power down bit is toggled.

        It is provided by the latest GEL file . I have learned from a document that one can know wether the main PLL is locked or not through  the state of RSV 20 pin.

        But I can't find the pin. Is there any register which has the same function as RSV 20 pin?

    3. Is it necessary to set the main PLL in bypass mode in my application?

     Thanks in advance.

    Best Regards,

    Nuoxi

     

  • 0 in reply to Nuoxi Lin
    TI__Guru* 84110 points

    Nuoxi,

    Without looking really close, my first question is why a PLL multiplication difference would not be needed since the input reference clock is 50MHz instead of 100MHz? Perhaps that does not matter until the loaded code starts running.

    My second question is whether you have implemented the PLL fix for the current silicon? This is done on the EVM using SPI address 0x51 and then it boots from SPI address 0x50 to load the actual program. For information on this, please see the errata document (go to TMS320C6678 and find the errata near the top). There are several threads on the forum about the PLL fix, also, which would explain it better than I can. And there may be some on the Wiki, too.

    Regards,
    RandyP