AM5708: AM5708 initialization problem

Hello Yuri,

Could you please share more information at what point in execution you are writing to these registers? Has IPU been fully initialized?

Are you writing your own GEL files or using the ones included with CCS?

Please see the following thread:

•  AM5708: Run Bare Metal Hello World on ARM Cortex-M4 

Might have related information.

-Josue

Hello, Josue!
Yes, the standard gel file is used. The sequence is as follows: the a15 core starts, the IPU is initialized via scripts, and then the emulator loads code that hangs while unicache is running (specifically, the emmc interface), making it impossible to halt and inspect the kernel. In another case, attempting to execute the code I provided above, even at the beginning of main() (HW_WR_REG32(0x55080000U +IPU_UNICACHE_MAINT, 0x00000010) results in kernel errors. Again, this doesn't happen on all boards. It's important for me to understand whether it's a hardware or software issue and what exactly is triggering it.

Hello Yuri, 

After reviewing the /ti/ccs1281/ccs/ccs_base/emulation/boards/am571x/gel/AM571x_multicore_reset.gel file, I noticed that the IPU initialization does not have the same "/* Start a SW force wakeup for DSPSS */", so maybe this is not a HW issue but a clk issue that somehow goes away after a reset. This would make it a SW bug.

Maybe you could try to add similar code to force the clks on:

WR_MEM_32(CM_IPU1_CLKSTCTRL,    0x2);                       // SW_WKUP
/* Enable IPUSS clock */
WR_MEM_32(CM_IPU1_IPU1_CLKCTRL, 0x1);
while ((RD_MEM_32(CM_IPU1_CLKSTCTRL) & 0x100) != 0x100);    // wait CLKACTIVITY_IPU1_GFCLK

Let me know if this helps. 

Otherwise please share a detailed procedure for reproduction on a TI device.

-Josue

Hello, Josue!
I used your code, and also made other changes and checks for enabling the IPU clock, but it didn't help. To describe it in more detail: after IPU initialization and loading code into it, it always starts. Moreover, if you don't use functions that work with unicache registers in the M4, the core hang will not occur. As soon as unicache is used, if it's a faulty start, the core will hang on the first access to these registers, with no ability to connect the emulator. If it doesn't hang, then subsequent accesses to unicache will also be fine and won't lead to a hang. I found a workaround for this hang. On error and core crash, you need to re-run the IPU initialization procedure from GEL and reload the code. If you perform IPU initialization several times at the beginning of operation, the error will still occur (if the start is faulty). It will only stop occurring if you start the core, realize there's an error on it, and reinitialize the IPU.

Hello,
Thank you for your inquiry. **Josue Zamitiz** is currently on leave and will be available on **2026-09-14**.
Your query will be addressed upon their return. We appreciate your patience and understanding.
Best regards,
TI E2E Support Team
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Hello Yuri,

I found the following guidance on the sequence we might be missing on these files.

So in an attempt to follow this procedure try inserting the following:

/* A15 cache init per TRM 3.5.6.8 Step 4, p.478 */
WR_MEM_32(IPU_MMU_CFG + 0x0014, 0x00000000);   /* CACHE_MTSTART = 0 */
WR_MEM_32(IPU_MMU_CFG + 0x0018, 0xFFFFFFFF);   /* CACHE_MTEND = all */
WR_MEM_32(IPU_MMU_CFG + 0x0010, 0x00000010);   /* CACHE_MAINT: INVALIDATE */
while ((RD_MEM_32(IPU_MMU_CFG + 0x0010) & 0x10) != 0);

 after the AMMU configuration and before WR_MEM_32(RM_IPU_RSTCTRL, 0x0).

-Josue

Helo, Josue!
I checked your suggestion, it doesn't help, but I noticed the following register: CACHE_INT 0x55080008. As a result, when starting via the M4 core emulator, no errors are visible in the registers; the error appears during code loading. After loading the code, if the register value changes to 0x00000110, then during further operation of the code with the IPU cache the core will hang. If it remains 0x0 as by default, then everything works. Resetting the register values, as well as changing the CACHE_CONFIG register setting, does not help

Yuri,

Thank you for the new information, as I look into this, I failed to ask you a fundamental question, is this being tested on TI boards or custom borards?

-Josue

Hello, Josue, this is a custom board

Yuri,

Does the same issue occur on a TI EVM? Do you have one to test on?

If you don't can you please share the exact procedure you are following including boot mode  and target configuration settings, CCS version etc.

-Josue