Other Parts Discussed in Thread: DM3730, SYSCONFIG
I'm having trouble configuring the DM8168 System MMU/DEMMU for the C674x DSP.
The ARM A8 is running Linux, and I have written a kernel driver to manage boot/init and IPC to the C674X DSP. It all works great until I add support to enable the DEMMU. For now, I intend to keep my DSP's physical and virtual address maps the same, and use the MMU to simply deny the DSP access to memory locations it does not own. Later, I will create DDR translations that allow me to align certain blocks to 16M page boundaries where I can manage caching for the entire page. I have experience with the DM3730, and successfully created a Linux kernel driver that managed boot/init and IPC to the IVA2, which included configuring the IVA2's MMU for memory protection and address space translation. I'm leverage concepts from that driver, as the MMU architectures of the DM3730 and DM816X look very similar.
Below, I describe my pseudo-code for h/w setup of the DM816X's DSP subsystem. Items in BOLD highlight those steps related to the DEMMU. I also describe unexpected behavior where observed.
1. Setup PRCM
1. Write SW_WKUP (2) to CM_ALWON_L3_SLOW_CLKSTCTRL
2. Read back CM_ALWON_L3_SLOW_CLKSTCTRL
3. Write MODULE_ENABLED (2) to CM_ALWON_CONTRL_CLKCTRL
4. Wait for [1:0] of CM_ALWON_CONTRL_CLKCTRL = 2
5. Write MODULE_ENABLED (2) to CM_ALWON_MCASP0_CLKCTRL
6. Wait for [1:0] of CM_ALWON_MCASP0_CLKCTRL = 2
7. Repeat 5-6 for MCASP1 and MCBSP.
8. Walk the list of GPTimers and enable any that are not already enabled.
9. Wait for CLOCK_ACTIVE [8] set in CM_ALWON_L3_SLOW_CLKSTCTRL.
10. Program MAINPLL_CTRL, MAINPLL_PWD, MAINPLL_FREQ1, MAINPLL_MDIV1, and MAINPLL_DIV7. (details available upon request).
11. Write 0 to DSPMEM_SLEEP and read back.
12. Write SW_WKUP (2) to CM_MMUCFG_CLKSTCTRL (0x48181410).
13. Write MODULE_ENABLED (2) to CM_ALWON_MMUCFG_CLKCTRL (0x481815A8).
14. Wait for IDLEST [17:16] of CM_ALWON_MMUCFG_CLKCTRL (0x481815A8) = 0.
15. Wait for CLKACTIVITY_MMU_GCLK [8] of CM_MMUCFG_CLKSTCTRL (0x48181410) set.
16. Write SW_WKUP (2) to CM_MMU_CLKSTCTRL (0x4818140C).
17. Write MODULE_ENABLED (2) to CM_ALWON_MMUDATA_CLKCTRL (0x4818159C).
18. Wait for IDLEST [17:16] of CM_ALWON_MMUDATA_CLKCTRL (0x4818159C) = 0.
19. Wait for CLKACTIVITY_MMU_GCLK [8] of CM_MMU_CLKSTCTRL (0x4818140C) set.
20. Write MODULE_ENABLED (2) to CM_ALWON_MAILBOX_CLKCTRL.
21. Wait for IDLEST [17:16] of CM_ALWON_MAILBOX_CLKCTRL = 0.
22. Write SW_WKUP (2) to CM_GEM_CLKSTCTRL.
23. Wait for INTRANSITION [20] = 0, [2:0] = 7 in PM_ACTIVE_PWRSTST.
24. Write MODULE_ENABLED (2) to CM_ACTIVE_GEM_CLKCTRL.
25. Wait for CLKACTIVITY for [10:8] in CM_GEM_CLKSTCTRL.
2. Setup IPC
1. Sets up mailbox stuff (details available upon request)
3. Force DSP Idle
1. Asserts DSP reset.
2. Sets bootaddr to base of L2RAM.
3. Programs self branch instructions in L2
4. Releases DSP reset. The DSP spins in L2.
4. DSP Start
1. Loads DSP binary to DDR.
2. Asserts DSP reset.
3. Sets DSPBOOTADDR to DSP binary base address.
4. Enable MMU.
1. Program TTB (details available upon request).
2. Set SOFTRESET [1] in MMU_SYSCONFIG (0x48010010).
3. Wait for MMU_RESETDONE [0] in MMU_SYSSTATUS (0x48010014).
4. Set MMU_SMARTIDLE [4:3] to 2 and MMU_AUTOIDLE [0] in MMU_SYSCONFIG (0x48010010).
5. Set MMU_TTB (0x4801004C) to base address of TTB.
6. Set MMU_INT handler.
7. Write 0x1F in MMU_IRQENABLE (0x4801001C).
8. Set MMU_TWLENABLE [2] and MMU_MMUENABLE [1] in MMU_CNTL (0x48010044).
5. Releases DSP reset - DSP boots.
With Steps 4.4 excluded, the boot sequence works great. But, the MMU is disabled. If I add steps 4.4 to enable the MMU, the DM8168 fails to set MMU_RESETDONE following the soft reset. If I exclude the soft reset, the system fails to boot. I haven't determined the state of the DSP in this case. If I exclude all of 4.4 except 4.4.4, then the DSP boot fails.
For now, I'm assuming the steps in setting up the TTB are ok. They should only enter into the equation when step 4.4.8 is run. But, I run into unexpected behavior simply by writing to the MMU_SYSCONFIG register in step 4.2. This implies a more fundamental problem like missing steps to prepare the MMU for configuration. However, the steps in 1.12 - 1.19 look right to me.
Can you see anything I'm missing?
Regards,
Matt