Part Number: TMS320C6746
Hello TI Support,
We are currently debugging an issue with the TMS320C6746 HPI16 interface when communicating with an NXP LS1043A RDB host processor.
We are using the HPI interface to implement a data queue between the DSP and the LS1043A host processor.
System configuration
- DSP: TMS320C6746
- Host processor: NXP LS1043A RDB
- Interface: TMS320C6746 HPI16
- Data exchange mechanism: Shared data queue through HPI
- Queue write pointer: Updated by the DSP
- Queue read pointer: Updated by the LS1043A host processor
- Host polling/processing interval: Every 2 ms using the LS1043A host processor timer
Issue description
The DSP continuously produces data and updates the write pointer of the data queue. The LS1043A periodically reads the queue pointers through HPI to determine whether new data is available.
The expected behavior is:
- DSP writes new data into the queue.
- DSP updates the write pointer.
- LS1043A reads the write pointer through HPI.
- LS1043A compares the write pointer with its read pointer.
- If the pointers are different, the host determines that new data is available and processes it.
- LS1043A then updates the read pointer after processing the data.
However, we are observing an intermittent issue where the DSP updates the write pointer, but the LS1043A does not observe the updated write-pointer value through HPI.
As a result, the LS1043A reads the write pointer as unchanged and assumes that no new data is available, even though the DSP has already updated the write pointer.
The host performs this queue/pointer processing every 2 ms using the LS1043A timer function.
Additional observation:
The memory location associated with the queue does not appear to have a basic memory integrity problem.
When we perform a dedicated memory read/write test on the same memory location/region where the issue was observed, the memory test passes successfully. We are able to write and read back the expected values during the memory test.
Observed behavior
DSP side:
- DSP successfully processes/produces new data.
- DSP updates the queue write pointer.
- The updated write-pointer value can be observed/verified on the DSP side.
LS1043A side:
- Host periodically reads the write pointer through HPI.
- In some instances, the host continues to read the previous write-pointer value.
- Therefore, the host concludes that no new data has been placed in the queue.
- The issue appears to be related to the visibility/reliability of the DSP-updated pointer value when accessed by the host through HPI.
Could you please advise whether there are any known issues, restrictions, or required synchronization mechanisms related to HPI16 reads of DSP-updated memory locations on the TMS320C6746?
In particular, we would like to understand:
- Is there any HPI read/prefetch/buffering behavior that could cause the LS1043A to read a stale value from a memory location that was recently updated by the DSP?
- Are there any required cache/memory synchronization or coherency operations on the C6746 side before updating a queue pointer that is subsequently read by the host through HPI?
- Are there any specific HPI timing requirements that could result in the host occasionally observing an old value?
- Are there any TMS320C6746 silicon errata or known HPI16 issues related to reading DSP-updated memory locations?
- Is there a recommended method for implementing a producer/consumer data queue between the C6746 DSP and an external HPI host to guarantee that pointer updates are correctly observed?
We can provide additional information such as the HPI configuration registers, memory/cache configuration, queue implementation, HPI timing parameters, and logic-analyzer captures if required.
Please let us know what additional information or measurements would be useful for debugging this issue.
Thanks.
