• State TI Thinks Resolved
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 206 views
  • Users 0 members are here
Support feedback
Options
Options
Related

AM623: DSS specification

Tony Tang
Mastermind 30777 points

Part Number: AM623

#1. The max pixel clock frequency is not same on data sheet and TRM, 165MHz or 200MHz is correct?

On datasheet, max is 165MHz.

Display subsystem
– Dual display support
– 1920x1080 @ 60fps for each display
– 1x 2048x1080 + 1x 1280x720
– Up to 165MHz pixel clock support with Independent PLL for each display

On TRM, max is 200MHz, 

Two display outputs
– Up to 24-bit per pixel arallel or embedded sync output
– Up to 200MHz pizel clock
– Supports
• 1920x1080@60fps
• 1x 2048x1080 + 1x 1280x720 (constrained by DDR bandwidth)

#2. Max line size and lines: 

#2.1. The LPP and PPL field are 12bit, supports 4096 lines and 4096 pixel per line, the line of  1920x1080@60fps should be 4096x4096 to state the max resolution supported by specification.

 #2.2. The next line specified the real use case given DDR bandwidth, it is doesn't give fps, it is not rigorous and cause confusing. 

image.png

  • 0
    TI__Genius 15910 points

    Hello Tony,

    Thank you for your query !

    Q1.

    Tony Tang said:
    The max pixel clock frequency is not same on data sheet and TRM, 165MHz or 200MHz is correct?

    Shortly, the AM62x Datasheet specified maximum 165 MHz pixel clock frequency is correct for the AM623 SoC.

    Tony Tang said:

    On datasheet, max is 165MHz.

    Display subsystem
    – Dual display support
    – 1920x1080 @ 60fps for each display
    – 1x 2048x1080 + 1x 1280x720
    – Up to 165MHz pixel clock support with Independent PLL for each display

    On TRM, max is 200MHz, 

    Two display outputs
    – Up to 24-bit per pixel arallel or embedded sync output
    – Up to 200MHz pizel clock
    – Supports
    • 1920x1080@60fps
    • 1x 2048x1080 + 1x 1280x720 (constrained by DDR bandwidth)

    A1: The TRM's DSS features list (200 MHz) describes the underlying DISPC IP block, which may be shared across multiple SoCs. The device-specific electrical limit is established by the Datasheet, and the AM62x TRM itself ( Section, DISPC Clocks) explicitly defers to the Datasheet for maximum frequency ratings:
    "For the maximum supported frequency ratings, refer to device-specific Datasheet."

    Q2. Max line size and lines: 

    Q2.1

    Tony Tang said:
    The LPP and PPL field are 12bit, supports 4096 lines and 4096 pixel per line, the line of  1920x1080@60fps should be 4096x4096 to state the max resolution supported by specification.


    The register fields confirm:
    • LPP (bits 27:16, 12-bit field): supports values 1 to 4096 lines per panel
    • PPL (bits 11:0, 12-bit field): supports values 1 to 4096 pixels per line
    So the hardware register capability is 4096×4096, and the "1920×1080@60fps" is indeed just one validated use-case example, not the hardware maximum. In the AM62x TRM /  Section, DISPC VP Timing Generator and Display Panel Settings confirms both fields support "a value from 1 to 4096".


    The datasheet's statement of "1920×1080@60fps" as a feature bullet is a representative use case, while the actual register max is 4096×4096. 

    Q2.2

    Tony Tang said:
    The next line specified the real use case given DDR bandwidth, it is doesn't give fps, it is not rigorous and cause confusing. 

    The datasheet feature line:
    "1x 2048x1080 + 1x 1280x720" ...does not specify a frame rate, which is ambiguous and potentially misleading, especially compared to the explicit "1920×1080@60fps" entry above it. The omission of the fps value for that configuration is due to the fact that the achievable frame rate is not a fixed number, it depends on the available DDR bandwidth, which is a system-level variable influenced by factors such as:
    • DDR data rate and bus width
    • Number of active DDR clients (CPU, GPU, other peripherals)
    • Memory access patterns and arbitration


    For this reason, rather than stating a specific fps that may not be achievable in all system configurations, the intent was to note the DDR bandwidth dependency. 
    As a general guideline, 60fps is achievable for both resolutions when DDR bandwidth is not otherwise constrained. For additional notes please refer the below excerpt from the below informative AM62x DSS related FAQ - https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1200847/faq-am625-am623-am620-q1-am625-q1-am625sip-am62p-am62p-q1-custom-board-hardware-design-oldi-open-lvds-display-interface-capabilities 

    I hope this helps you clarify !

    Best Regards,

    Anastas Yordanov

  • 0 in reply to Anastas Yordanov
    TI__Mastermind 30777 points

    Hello Anastas,

    Thanks for clarification, but the datasheet still confuse customer not me, I knew the background very well,  as you saw there are customers ask this bullet from time to time, and need a FAQ to explain it although customers didn't notice the FAQ before asking question.

    I would suggest to modify to like this:

    Display subsystem
    – Dual display support
    – 4096x4096 maximum resolution for each display
    – 1x 2048x1080@60fps + 1x 1280x720 @60fps with typical DDR loading
    – Up to 165MHz pixel clock support with Independent PLL for each display

    And the original statement are confliction, first one is 1920x1080 @60fps, but next line 2048x1080 which larger than 1920x1080, since can support 2048x1080@60fps, why emphasis 1920x1080@60fps for each display.

    If it doesn't mean 2048x1080 @60fps, then it can be any resolution combination.

  • 0 in reply to Tony Tang
    TI__Genius 15910 points

    Hi Tony,

    I suspect that the support even of 1 link x 2048 x1080 at 60 fps may have stronger dependency on the DDR4 and can be only guaranteed at certain DDR settings. I shall discuss back with the hardware spec. owner and Datasheet team before any updates in the documentation. I will keep you updated.

    Thank you

    Best Regards,

    Anastas Yordanov

  • 0 in reply to Anastas Yordanov
    TI__Genius 15910 points

    Hi Tony,

    Here is the argumentation from the AM62x DSS hardware expert:

    " With AM62x’s 16-bit wide DDR interface with a maximum supported DDR CLK frequency of 800MHz (1600MT/s), the peak supported BW would be

    800MHz * 4 = 3.2GBps. If we account for overhead, the peak BW can be reduced by ~25% potentially. If we then assume the standard 32-bit color depth is used with 1080p at 60fps (Full HD), this could mean close to 1GBps might be needed, and then the CPU/GPU activities could also take around 1Gbps or more. This means that increasing the resolution and/or fps could prevent the DSS from continuously transmitting video to the external display. Another limitation is that the DSS subsystem was enclosed for a maximum pixel clock frequency of 165MHz."

    Please let me know if this clarifies and we can close the thread.

    Thank you !

    Best Regards,

    Anastas Yordanov

  • 0 in reply to Anastas Yordanov
    TI__Genius 15910 points

    Hi Tony,

    Would you please input the customer request as provided per email to me in the thread ?

    Thank you !

    Best Regards,

    Anastas Yordanov

  • 0 in reply to Anastas Yordanov
    TI__Mastermind 30777 points

    With current datasheet specification, customer has many questions need to clarify:

    #1. What is the maximum resolution can be supported disregard fresh rate?

    #2. What is 1x2048x1080 +1x1280x720 means here, can it be other resolution combination? What fps can be supported?

    #3. If two 1920x1080@30fps can be supported?

    #4. If 2160x1080@60fps panel can be supported?

     

    I hope these questions can be answered by datasheet spec itself as we can’t touch every customer.

  • 0 in reply to Tony Tang
    TI__Genius 15910 points

    Hi Tony,

    I will let our Sitara Processors DSS hardware expert check and confirm once again.

    Please allow him some time.

    Thank you for your patience !

    Best Regards,

    Anastas Yordanov