TDA4VL-Q1: Boot Issue While Adding CAN Profiling in Vision App

Part Number: TDA4VL-Q1
Other Parts Discussed in Thread: TDA4VL

Hi Team,

I am trying to add CAN profiling to the Vision application to verify whether the CAN is functioning correctly. However, I am facing a boot issue after adding the CAN profiling.

Could you please help me identify the cause of the boot issue and suggest the appropriate steps to resolve it?

Kindly find the attached log.

Boot_log.txt 

  • Hi Indumathi,

    Error looks to be similar to this thread:  TDA4AL-Q1: [FreeRTOS]Timeout waiting for thread SP_RESPONSE to fill 

    Looks to be issues with sciserver integration and/or perhaps using ipc_rtos_echo_test"b"_freertos vs ipc_rtos_echo_test_freertos application as the base.

    Could you review the similar thread and see if any of the suggestions in the other thread work?

    Regards,

    Takuma

  • Hi,

    I followed the above link and ran the IPC from the following path : /home/user/Documents/TDA4VL/ti-processor-sdk-rtos-j721s2-evm-11_02_01_03/pdk_j721s2_11_02_01_08/packages/ti/build

    The boot process is working. However, When i try to run vision application i am getting IPC related error.

    Could you please review the attached error log and help identify the root cause?

    j721s2-evm login: root
    [   24.687065] audit: type=1006 audit(1748560126.568:15): pid=1016 uid=0 subj=kernel old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=2 res=1
    [   24.701087] audit: type=1300 audit(1748560126.568:15): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=ffffef363718 a2=1 a3=1 items=0 ppid=1 pid=1016 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid)
    [   24.729097] audit: type=1327 audit(1748560126.568:15): proctitle="(systemd)"
    [   24.740527] audit: type=1334 audit(1748560126.624:16): prog-id=18 op=LOAD
    [   24.747352] audit: type=1300 audit(1748560126.624:16): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffc42120d8 a2=90 a3=0 items=0 ppid=1 pid=1016 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 eg)
    [   24.774172] audit: type=1327 audit(1748560126.624:16): proctitle="(systemd)"
    [   24.781245] audit: type=1334 audit(1748560126.624:17): prog-id=18 op=UNLOAD
    [   24.788260] audit: type=1300 audit(1748560126.624:17): arch=c00000b7 syscall=57 success=yes exit=0 a0=8 a1=1 a2=0 a3=ffffa75ec400 items=0 ppid=1 pid=1016 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid)
    [   24.815292] audit: type=1327 audit(1748560126.624:17): proctitle="(systemd)"
    [   24.822804] audit: type=1334 audit(1748560126.624:18): prog-id=19 op=LOAD
    root@j721s2-evm:~# cd /opt/vision_apps/
    root@j721s2-evm:/opt/vision_apps# source ./vision_apps_init.sh 
    root@j721s2-evm:/opt/vision_apps# [MCU2_0]      5.612855 s: CIO: Init ... Done !!!
    [MCU2_0]      5.612905 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_0]      5.612931 s: CPU is running FreeRTOS
    [MCU2_0]      5.612948 s: APP: Init ... !!!
    [MCU2_0]      5.612989 s: SCICLIENT: Init ... !!!
    [MCU2_0]      5.613115 s: SCICLIENT: DMSC FW version [11.2.13--v11.02.13 (Fancy Rat)]
    [MCU2_0]      5.613144 s: SCICLIENT: DMSC FW revision 0xb  
    [MCU2_0]      5.613164 s: SCICLIENT: DMSC FW ABI revision 4.0
    [MCU2_0]      5.613185 s: SCICLIENT: Init ... Done !!!
    [MCU2_0]      5.613202 s: UDMA: Init ... !!!
    [MCU2_0]      5.614016 s: UDMA: Init ... Done !!!
    [MCU2_0]      5.614044 s: UDMA: Init for CSITX/CSIRX ... !!!
    [MCU2_0]      5.614467 s: UDMA: Init for CSITX/CSIRX ... Done !!!
    [MCU2_0]      5.614496 s: MEM: Init ... !!!
    [MCU2_0]      5.614520 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000000) @ b9000000 of size 14680064 bytes with alignment: 256 !!!
    [MCU2_0]      5.614569 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 524288 bytes with alignment: 256 !!!
    [MCU2_0]      5.614612 s: MEM: Created heap (DDR_CACHE_WT_ME, id=7, flags=0x00000000) @ b9e00000 of size 2097152 bytes with alignment: 256 !!!
    [MCU2_0]      5.614653 s: MEM: Init ... Done !!!
    [MCU2_0]      5.614669 s: IPC: Init ... !!!
    [MCU2_0]      5.614708 s: IPC: 8 CPUs participating in IPC !!!
    [MCU2_0]      5.614736 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU2_0]     18.377331 s: IPC: HLOS is ready !!!
    [MCU2_0]     18.382511 s: IPC: Init ... Done !!!
    [MCU2_0]     18.382549 s: APP: Syncing with 7 CPUs ... !!!
    [MCU2_1]      5.667467 s: CIO: Init ... Done !!!
    [MCU2_1]      5.667517 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_1]      5.667540 s: CPU is running FreeRTOS
    [MCU2_1]      5.667556 s: APP: Init ... !!!
    [MCU2_1]      5.667594 s: SCICLIENT: Init ... !!!
    [MCU2_1]      5.667711 s: SCICLIENT: DMSC FW version [11.2.13--v11.02.13 (Fancy Rat)]
    [MCU2_1]      5.667738 s: SCICLIENT: DMSC FW revision 0xb  
    [MCU2_1]      5.667757 s: SCICLIENT: DMSC FW ABI revision 4.0
    [MCU2_1]      5.667777 s: SCICLIENT: Init ... Done !!!
    [MCU2_1]      5.667795 s: UDMA: Init ... !!!
    [MCU2_1]      5.668636 s: UDMA: Init ... Done !!!
    [MCU2_1]      5.668664 s: MEM: Init ... !!!
    [MCU2_1]      5.668690 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000000) @ ba000000 of size 16777216 bytes with alignment: 256 !!!
    [MCU2_1]      5.668740 s: MEM: Init ... Done !!!
    [MCU2_1]      5.668758 s: IPC: Init ... !!!
    [MCU2_1]      5.668789 s: IPC: 8 CPUs participating in IPC !!!
    [MCU2_1]      5.668817 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU2_1]     18.537583 s: IPC: HLOS is ready !!!
    [MCU2_1]     18.542567 s: IPC: Init ... Done !!!
    [MCU2_1]     18.542607 s: APP: Syncing with 7 CPUs ... !!!
    [MCU3_0]      5.730218 s: CIO: Init ... Done !!!
    [MCU3_0]      5.730270 s: ### CPU Frequency = 1000000000 Hz
    [MCU3_0]      5.730295 s: CPU is running FreeRTOS
    [MCU3_0]      5.730312 s: APP: Init ... !!!
    [MCU3_0]      5.730346 s: SCICLIENT: Init ... !!!
    [MCU3_0]      5.730465 s: SCICLIENT: DMSC FW version [11.2.13--v11.02.13 (Fancy Rat)]
    [MCU3_0]      5.730496 s: SCICLIENT: DMSC FW revision 0xb  
    [MCU3_0]      5.730516 s: SCICLIENT: DMSC FW ABI revision 4.0
    [MCU3_0]      5.730536 s: SCICLIENT: Init ... Done !!!
    [MCU3_0]      5.730554 s: MEM: Init ... !!!
    [MCU3_0]      5.730577 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000000) @ bb000000 of size 8388608 bytes with alignment: 256 !!!
    [MCU3_0]      5.730623 s: MEM: Init ... Done !!!
    [MCU3_0]      5.730640 s: IPC: Init ... !!!
    [MCU3_0]      5.730670 s: IPC: 8 CPUs participating in IPC !!!
    [MCU3_0]      5.730699 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU3_0]     18.719537 s: IPC: HLOS is ready !!!
    [MCU3_0]     18.724331 s: IPC: Init ... Done !!!
    [MCU3_0]     18.724367 s: APP: Syncing with 7 CPUs ... !!!
    [MCU3_1]      5.797136 s: CIO: Init ... Done !!!
    [MCU3_1]      5.797189 s: ### CPU Frequency = 1000000000 Hz
    [MCU3_1]      5.797212 s: CPU is running FreeRTOS
    [MCU3_1]      5.797228 s: APP: Init ... !!!
    [MCU3_1]      5.797262 s: SCICLIENT: Init ... !!!
    [MCU3_1]      5.797381 s: SCICLIENT: DMSC FW version [11.2.13--v11.02.13 (Fancy Rat)]
    [MCU3_1]      5.797409 s: SCICLIENT: DMSC FW revision 0xb  
    [MCU3_1]      5.797429 s: SCICLIENT: DMSC FW ABI revision 4.0
    [MCU3_1]      5.797449 s: SCICLIENT: Init ... Done !!!
    [MCU3_1]      5.797467 s: MEM: Init ... !!!
    [MCU3_1]      5.797489 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000000) @ bb800000 of size 8388608 bytes with alignment: 256 !!!
    [MCU3_1]      5.797536 s: MEM: Init ... Done !!!
    [MCU3_1]      5.797553 s: IPC: Init ... !!!
    [MCU3_1]      5.797584 s: IPC: 8 CPUs participating in IPC !!!
    [MCU3_1]      5.797613 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU3_1]     18.794074 s: IPC: HLOS is ready !!!
    [MCU3_1]     18.798702 s: IPC: Init ... Done !!!
    [MCU3_1]     18.798737 s: APP: Syncing with 7 CPUs ... !!!
    [C7x_1 ]      6.032580 s: CIO: Init ... Done !!!
    [C7x_1 ]      6.032597 s: ### CPU Frequency = 1000000000 Hz
    [C7x_1 ]      6.032610 s: CPU is running FreeRTOS
    [C7x_1 ]      6.032619 s: APP: Init ... !!!
    [C7x_1 ]      6.032628 s: SCICLIENT: Init ... !!!
    [C7x_1 ]      6.032731 s: SCICLIENT: DMSC FW version [11.2.13--v11.02.13 (Fancy Rat)]
    [C7x_1 ]      6.032746 s: SCICLIENT: DMSC FW revision 0xb  
    [C7x_1 ]      6.032758 s: SCICLIENT: DMSC FW ABI revision 4.0
    [C7x_1 ]      6.032769 s: SCICLIENT: Init ... Done !!!
    [C7x_1 ]      6.032779 s: UDMA: Init ... !!!
    [C7x_1 ]      6.033537 s: UDMA: Init ... Done !!!
    [C7x_1 ]      6.033552 s: MEM: Init ... !!!
    [C7x_1 ]      6.033564 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000000) @ 117000000 of size 268435456 bytes with alignment: 256 !!!
    [C7x_1 ]      6.033590 s: MEM: Init ... Done !!!
    [C7x_1 ]      6.033600 s: IPC: Init ... !!!
    [C7x_1 ]      6.033616 s: IPC: 8 CPUs participating in IPC !!!
    [C7x_1 ]      6.033631 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_1 ]     18.054762 s: IPC: HLOS is ready !!!
    [C7x_1 ]     18.057636 s: IPC: Init ... Done !!!
    [C7x_1 ]     18.057653 s: APP: Syncing with 7 CPUs ... !!!
    [C7x_2 ]      6.128371 s: CIO: Init ... Done !!!
    [C7x_2 ]      6.128389 s: ### CPU Frequency = 1000000000 Hz
    [C7x_2 ]      6.128402 s: CPU is running FreeRTOS
    [C7x_2 ]      6.128414 s: APP: Init ... !!!
    [C7x_2 ]      6.128423 s: SCICLIENT: Init ... !!!
    [C7x_2 ]      6.128530 s: SCICLIENT: DMSC FW version [11.2.13--v11.02.13 (Fancy Rat)]
    [C7x_2 ]      6.128546 s: SCICLIENT: DMSC FW revision 0xb  
    [C7x_2 ]      6.128558 s: SCICLIENT: DMSC FW ABI revision 4.0
    [C7x_2 ]      6.128570 s: SCICLIENT: Init ... Done !!!
    [C7x_2 ]      6.128582 s: UDMA: Init ... !!!
    [C7x_2 ]      6.129336 s: UDMA: Init ... Done !!!
    [C7x_2 ]      6.129351 s: MEM: Init ... !!!
    [C7x_2 ]      6.129363 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000000) @ 127000000 of size 16777216 bytes with alignment: 256 !!!
    [C7x_2 ]      6.129390 s: MEM: Init ... Done !!!
    [C7x_2 ]      6.129401 s: IPC: Init ... !!!
    [C7x_2 ]      6.129418 s: IPC: 8 CPUs participating in IPC !!!
    [C7x_2 ]      6.129436 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_2 ]     18.174597 s: IPC: HLOS is ready !!!
    [C7x_2 ]     18.177346 s: IPC: Init ... Done !!!
    [C7x_2 ]     18.177365 s: APP: Syncing with 7 CPUs ... !!!
    
    root@j721s2-evm:/opt/vision_apps# ./run_app_tidl.sh 
    APP: Init ... !!!
        89.437068 s: MEM: Init ... !!!
        89.437148 s: MEM: Initialized DMA HEAP (fd=4) !!!
        89.437333 s: MEM: Init ... Done !!!
        89.437354 s: IPC: Init ... !!!
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio0.rpmsg_chrdev.-1.13
        89.472431 s: IPC: ERROR: Unable to create TX channels for CPU [mcu1_0] !!!
        89.472530 s: IPC: Init ... Done !!!
    APP: ERROR: IPC init failed !!!
    REMOTE_SERVICE: Init ... !!!
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio0.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio3.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio4.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio5.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio6.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio1.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio2.rpmsg_chrdev.-1.21
    REMOTE_SERVICE: Init ... Done !!!
        89.481469 s: GTC Frequency = 200 MHz
    APP: Init ... Done !!!
        89.489825 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
        89.489871 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
        89.489879 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
        89.491989 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 
        89.492190 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 
        89.492303 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 
        89.492394 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 
        89.492408 s: VX_ZONE_INFO: [tivxInitLocal:202] Initialization Done !!!
        89.492420 s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
        89.496410 s: VX_ZONE_ERROR: [ownContextCreateCmdObj:171] context object descriptor [0] allocation failed
        89.496442 s: VX_ZONE_ERROR: [ownContextCreateCmdObj:174] context object descriptor [0] allocation failed
        89.496451 s: VX_ZONE_ERROR: [ownContextCreateCmdObj:175] Exceeded max object descriptors available.
        89.496463 s: VX_ZONE_ERROR: [ownContextCreateCmdObj:176] May need to increase the value of TIVX_PLATFORM_MAX_OBJ_DESC_SHM_INST in include/TI/soc/tivx_config_j721s2.h
        89.496491 s: VX_ZONE_ERROR: [vxCreateContext:1227] context objection creation failed
        89.496528 s: VX_ZONE_ERROR: [ownIsKernelInContext:732] Failed to lock context
        89.496538 s: VX_ZONE_ERROR: [ownGetErrorObject:55] Failed to lock context
        89.496548 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.496662 s: VX_ZONE_ERROR: [vxLoadKernels:225] Publish function for module openvx-core failed
    app_tidl: ERROR: Unable to open IO config file /opt/vision_apps/test_data/tivx/tidl_models/tidl_io_mobilenet_v1_1.bin 
    app_tidl: ERROR: Unable to open network file /opt/vision_apps/test_data/tivx/tidl_models/tidl_net_mobilenet_v1.bin 
        89.502003 s: VX_ZONE_ERROR: [ownIncrementReference:763] Failed to lock reference 
        89.502021 s: VX_ZONE_ERROR: [ownAddReferenceToContext:422] Failed to lock context
        89.502030 s: VX_ZONE_ERROR: [ownCreateReference:874] Add reference to context failed
        89.502047 s: VX_ZONE_ERROR: [ownCreateReference:884] Failed to add to resources table
        89.502055 s: VX_ZONE_ERROR: [ownGetErrorObject:55] Failed to lock context
        89.502062 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.502072 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.502082 s: VX_ZONE_ERROR: [ownIncrementReference:763] Failed to lock reference 
        89.502090 s: VX_ZONE_ERROR: [ownAddReferenceToContext:422] Failed to lock context
        89.502098 s: VX_ZONE_ERROR: [ownCreateReference:874] Add reference to context failed
        89.502106 s: VX_ZONE_ERROR: [ownCreateReference:884] Failed to add to resources table
        89.502114 s: VX_ZONE_ERROR: [ownGetErrorObject:55] Failed to lock context
        89.502121 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.502129 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.502137 s: VX_ZONE_ERROR: [ownIncrementReference:763] Failed to lock reference 
        89.502144 s: VX_ZONE_ERROR: [ownAddReferenceToContext:422] Failed to lock context
        89.502152 s: VX_ZONE_ERROR: [ownCreateReference:874] Add reference to context failed
        89.502160 s: VX_ZONE_ERROR: [ownCreateReference:884] Failed to add to resources table
        89.502167 s: VX_ZONE_ERROR: [ownGetErrorObject:55] Failed to lock context
        89.502174 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.838977 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.839005 s: VX_ZONE_ERROR: [vxGetKernelByName:2132] Failed to lock context
        89.839017 s: VX_ZONE_ERROR: [vxAllocateUserKernelId:2016] Failed to lock context
        89.839025 s: VX_ZONE_ERROR: [tivxAddKernelTIDL:274] Unable to allocate user kernel ID
        89.839096 s: VX_ZONE_ERROR: [ownIncrementReference:763] Failed to lock reference 
        89.839107 s: VX_ZONE_ERROR: [ownAddReferenceToContext:422] Failed to lock context
        89.839114 s: VX_ZONE_ERROR: [ownCreateReference:874] Add reference to context failed
        89.839125 s: VX_ZONE_ERROR: [ownCreateReference:884] Failed to add to resources table
        89.839133 s: VX_ZONE_ERROR: [ownGetErrorObject:55] Failed to lock context
        89.839141 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.839151 s: VX_ZONE_ERROR: [ownIncrementReference:763] Failed to lock reference 
        89.839159 s: VX_ZONE_ERROR: [ownAddReferenceToContext:422] Failed to lock context
        89.839166 s: VX_ZONE_ERROR: [ownCreateReference:874] Add reference to context failed
        89.839174 s: VX_ZONE_ERROR: [ownCreateReference:884] Failed to add to resources table
        89.839182 s: VX_ZONE_ERROR: [ownGetErrorObject:55] Failed to lock context
        89.839189 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.839239 s: VX_ZONE_ERROR: [vxAllocateUserKernelId:2016] Failed to lock context
        89.839248 s: VX_ZONE_ERROR: [tivxAddKernelDisplay:202] Unable to allocate user kernel ID
        89.839257 s: VX_ZONE_ERROR: [vxLoadKernels:225] Publish function for module video_io failed
        89.839269 s: VX_ZONE_ERROR: [vxAllocateUserKernelId:2016] Failed to lock context
        89.839277 s: VX_ZONE_ERROR: [tivxAddKernelTIDLV2:471] Unable to allocate user kernel ID
        89.839285 s: VX_ZONE_ERROR: [vxLoadKernels:225] Publish function for module tidl failed
        89.853445 s: VX_ZONE_ERROR: [tivx_utils_bmp_read:869] Failed to open file </opt/vision_apps/test_data/tivx/tidl_models/ti_logo.bmp>.
        89.864302 s: VX_ZONE_ERROR: [ownAddReferenceToContext:422] Failed to lock context
        89.864335 s: VX_ZONE_ERROR: [ownCreateReference:874] Add reference to context failed
        89.864347 s: VX_ZONE_ERROR: [ownCreateReference:884] Failed to add to resources table
        89.864356 s: VX_ZONE_ERROR: [ownGetErrorObject:55] Failed to lock context
        89.864365 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.864376 s: VX_ZONE_ERROR: [vxSetReferenceName:1239] Invalid reference
        89.864393 s: VX_ZONE_ERROR: [vxQueryKernel:168] Invalid kernel reference
        89.864408 s: VX_ZONE_ERROR: [vxMapUserDataObject:471] Invalid user data object reference
        89.864419 s: VX_ZONE_ERROR: [vxUnmapUserDataObject:564] Invalid user data object reference
        89.864436 s: VX_ZONE_ERROR: [vxAddLogEntry:62] Invalid reference!
        89.864445 s: VX_ZONE_ERROR: [vxCreateNodeByStructure:84] failed to retrieve kernel enum 0
        89.864468 s: VX_ZONE_ERROR: [ownAddReferenceToContext:422] Failed to lock context
        89.864477 s: VX_ZONE_ERROR: [ownCreateReference:874] Add reference to context failed
        89.864485 s: VX_ZONE_ERROR: [ownCreateReference:884] Failed to add to resources table
        89.864492 s: VX_ZONE_ERROR: [ownGetErrorObject:55] Failed to lock context
        89.864500 s: VX_ZONE_ERROR: [vxGetStatus:1294] Reference is NULL
        89.864507 s: VX_ZONE_ERROR: [vxSetReferenceName:1239] Invalid reference
        89.864520 s: VX_ZONE_ERROR: [tivxCreateNodeByKernelName:122] Call to vxGetKernelByName failed; kernel may not be registered
        89.864529 s: VX_ZONE_ERROR: [vxSetReferenceName:1239] Invalid reference
        89.864536 s: VX_ZONE_ERROR: [vxSetReferenceName:1239] Invalid reference
        89.864543 s: VX_ZONE_ERROR: [vxSetReferenceName:1239] Invalid reference
        89.864550 s: VX_ZONE_ERROR: [vxSetReferenceName:1239] Invalid reference
        89.864558 s: VX_ZONE_ERROR: [vxSetReferenceName:1239] Invalid reference
        89.864565 s: VX_ZONE[   81.928402] kauditd_printk_skb: 5 callbacks suppressed
    _ERROR: [vxSetReferenceName:1239] Invalid reference
        89.8645[   81.928414] audit: type=1701 audit(1748560183.812:20): auid=4294967295 uid=0 gid=0 ses=4294967295 subj=kernel pid=1040 comm="vx_app_tidl.out" exe="/opt/vision_apps/vx_app_tidl.out" sig=11 1
    72 s: VX_ZONE_ERROR: [vxSetReferenceName:1239] Invalid reference[   81.959902] audit: type=1334 audit(1748560183.844:21): prog-id=20 op=LOAD
    
        90.199817 s: VX_ZONE_ERROR: [vxSetReferenceName:1239] Inva[   81.972089] audit: type=1334 audit(1748560183.856:22): prog-id=21 op=LOAD
    lid reference
        90.199829 s: VX_ZONE_ERROR: [vxSetReferenceNa[   81.984380] audit: type=1334 audit(1748560183.868:23): prog-id=22 op=LOAD
    me:1239] Invalid reference
        90.199841 s: VX_ZONE_ERROR: [vxVerifyGraph:2486] Invalid graph reference
        90.199849 s: VX_ZONE_ERROR: [vxVerifyGraph:2814] Invalid graph reference
    app_tidl: ERROR: Verifying graph ... Failed !!!
        90.199879 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199891 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199899 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199906 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199918 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199926 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199933 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199940 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199947 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199960 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199967 s: VX_ZONE_ERROR: [ownReleaseReferenceInt:847] Invalid reference
        90.199981 s: VX_ZONE_ERROR: [vxUnloadKernels:275] Unable to unload kernels for module tidl
        90.199998 s: VX_ZONE_ERROR: [vxUnloadKernels:275] Unable to unload kernels for module video_io
        90.200012 s: VX_ZONE_ERROR: [vxRemoveKernel:320] Invalid kernel reference
        90.200025 s: VX_ZONE_ERROR: [ownDecrementReference:720] Failed to lock reference 
        90.207353 s: VX_ZONE_ERROR: [ownPosixObjectDeInit:340] Deiniting mutex at index: 10 failed
    APP: Deinit ... !!!
    REMOTE_SERVICE: Deinit ... !!!
        90.207404 s: IPC: ERROR: Failed to close created endpoint !!!
        90.207412 s: IPC: ERROR: Failed to close created endpoint !!!
        90.207418 s: IPC: ERROR: Failed to close created endpoint !!!
        90.207425 s: IPC: ERROR: Failed to close created endpoint !!!
        90.207431 s: IPC: ERROR: Failed to close created endpoint !!!
        90.207437 s: IPC: ERROR: Failed to close created endpoint !!!
        90.207444 s: IPC: ERROR: Failed to close created endpoint !!!
    REMOTE_SERVICE: Deinit ... Done !!!
        90.207456 s: IPC: Deinit ... !!!
    ./run_app_tidl.sh: line 1:  1040 Segmentation fault      (core dumped) /opt/vision_apps/vx_app_tidl.out --cfg app_oc.cfg
    root@j721s2-evm:/opt/vision_apps# [   83.360163] audit: type=1334 audit(1748560185.244:24): prog-id=22 op=UNLOAD
    [   83.367409] audit: type=1334 audit(1748560185.244:25): prog-id=21 op=UNLOAD
    [   83.374393] audit: type=1334 audit(1748560185.244:26): prog-id=20 op=UNLOAD
    
    

  • Hi Indumathi,

    Looks like an issue with remote core images. Could you review this developer note to see if the new generated files were integrated into U-Boot and whether a step was missed? https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j721s2/11_02_01_03/exports/docs/psdk_rtos/docs/user_guide/developer_notes_mcu1_0_sysfw.html

    Specifically, "9.3.3.3. SPL/uboot Loading" section?

    Regards,

    Takuma

  • Hi Takuma,

    The boot process itself was failing before I followed the “SPL/u-boot Loading” steps. After following those steps, the boot process completed successfully; however, the Vision Apps are now failing with an IPC error.

    Note: The DM parameter has been updated with the newly generated firmware, and the same firmware has been copied to:

    /lib/firmware/j7-mcu-r5f0_0-fw

    Regards,

    M Indumathi

  • Hi Indumathi,

    To clarify, was only the firmware updated with new copy, or was U-Boot and tispl.bin image also updated on the SD card?

    Specifically, these lines from section 9.3.3.3:

    "As mentioned in the introduction, when using SPL/uboot, the tispl.bin generation step is now dependent on the compiled MCU1_0 firmware image. So each time the MCU1_0 image is regenerated, the uboot and tispl.bin also need to be regenerated as part of the build flow. Likewise, if the uboot or tispl.bin need to be rebuilt, then the user needs to pass the appropriate MCU1_0 firmware image to the uboot build command."

    Regards,

    Takuma

  • Hi Takuma,

    Yes, the U-Boot and tispl.bin images were also updated on the SD card. I copied the U-Boot and tispl.bin images from the following path:

    /home/$user/ti-processor-sdk-linux-adas-j721s2-evm-11_02_01_03/board-support/ti-u-boot-2025.01+git/build/a72

    However, even after following all the required steps and updating the images, the IPC error still occurs.

    Regards,

    M Indumathi

  • Hi Indumathi,

    Could you share the link for any guide that was followed to create the SD card, and also the steps (and/or patches) done to modify the default SD card.

    I will try to see if I can replicate the error on my end. In addition to above, any additional information that may help in replicating the issue will be much appreciated.

    Regards,

    Takuma

  • Hi Indumathi,

    Apologies for the back and forth. For the CAN profiling addition, any documentation that was followed, and/or any patches? And also what build command/flash procedures that were followed?

    Regards,

    Takuma

  • Hi Takuma,

    We followed the patch 8.2 and applied the steps as well from the below ticket 

     [FAQ] TDA4VM: MCUSW demo on CAN along side Linux on A72 

    In Step 2.2 from above patch, Instead of make can_profile_app BUILD_OS_TYPE=tirtos CORE=mcu1_0 we  used make -s can_profile_app BOARD=j721s2_evm SOC=j721s2 BUILD_PROFILE=release CORE=mcu1_0 BUILD_OS_TYPE=freertos.

    Kindly let me know if more information is required.

    Regards,

    M Indumathi

  • Hi Indumathi,

    Thanks. That should be enough to reproduce the setup. Will try it out on Monday.

    Regards,

    Takuma

  • Hi Indumathi,

    For your setup, is it using 11.2.1.3 SDK version as the base image? I am finding the patches not applying cleanly.

    And have you tested with 8.2 SDK as the base?

    Regards,

    Takuma

  • Hi Takuma,

    For your setup, is it using 11.2.1.3 SDK version as the base image? - yes, i am using v11.2.1.3 sdk

    And have you tested with 8.2 SDK as the base?  - i applied the 8.2 patch into above sdk.

    Kindly find th eattached main_rtos.c and linker_r5_freertos.lds files where the patched were applied.

    /*
    *
    * Copyright (c) 2024-2020 Texas Instruments Incorporated
    *
    * All rights reserved not granted herein.
    *
    * Limited License.
    *
    * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
    * license under copyrights and patents it now or hereafter owns or controls to make,
    * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
    * terms herein.  With respect to the foregoing patent license, such license is granted
    * solely to the extent that any such patent is necessary to Utilize the software alone.
    * The patent license shall not apply to any combinations which include this software,
    * other than combinations with devices manufactured by or for TI ("TI Devices").
    * No hardware patent is licensed hereunder.
    *
    * Redistributions must preserve existing copyright notices and reproduce this license
    * (including the above copyright notice and the disclaimer and (if applicable) source
    * code license limitations below) in the documentation and/or other materials provided
    * with the distribution
    *
    * Redistribution and use in binary form, without modification, are permitted provided
    * that the following conditions are met:
    *
    * *       No reverse engineering, decompilation, or disassembly of this software is
    * permitted with respect to any software provided in binary form.
    *
    * *       any redistribution and use are licensed by TI for use only with TI Devices.
    *
    * *       Nothing shall obligate TI to provide you with source code for the software
    * licensed and provided to you in object code.
    *
    * If software source code is provided to you, modification and redistribution of the
    * source code are permitted provided that the following conditions are met:
    *
    * *       any redistribution and use of the source code, including any resulting derivative
    * works, are licensed by TI for use only with TI Devices.
    *
    * *       any redistribution and use of any object code compiled from the source code
    * and any resulting derivative works, are licensed by TI for use only with TI Devices.
    *
    * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
    *
    * may be used to endorse or promote products derived from this software without
    * specific prior written permission.
    *
    * DISCLAIMER.
    *
    * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
    * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
    * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
    * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
    * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
    * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
    * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
    * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
    * OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    */
    
    /**
     *  \file can_profile.h.c
     *
     *  \brief Main file for TI-RTOS build
     */
    
    /* ========================================================================== */
    /*                             Include Files                                  */
    /* ========================================================================== */
    
    #include <ti/csl/arch/csl_arch.h>
    #include <ti/csl/soc.h>
    #include <ti/csl/cslr.h>
    
    #include <ti/osal/osal.h>
    #include <ti/osal/TaskP.h>
    
    #include "CanApp_Startup.h"
    #include "can_profile.h"
    #include "CanIf.h"
    #if (defined (BUILD_MCU1_0) && (defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J784S4) || defined (SOC_J721S2) || defined (SOC_J742S2)))
    #include <ti/drv/sciclient/sciserver_tirtos.h>
    #endif
    #include <ti/drv/ipc/include/ipc_rsctypes.h>
    #include <ti/drv/sciclient/sciclient.h>
    //#include <ti/drv/pm/examples/utils/app_utils.h>
    /* ========================================================================== */
    /*                           Macros & Typedefs                                */
    /* ========================================================================== */
    
    /* Test application stack size */
    #define APP_TASK_STACK                  (10U * 1024U)
    /**< Stack required for the stack */
    #define CAN_PROFILE_DEMO_TASK_NAME      ("CAN PROFILE")
    /**< Task name */
    /*Added*/
    #define APP_TSK_STACK_MAIN              (32U * 1024U)
    /**< Test application stack size */
    #define IPC_INIT_SCISERVER_TASK_PRI         (6)
    #define APP_SCISERVER_INIT_TSK_STACK        (32U * 1024U)
    /* High Priority for SCI Server - must be higher than Low priority task */
    #define IPC_SETUP_SCISERVER_TASK_PRI_HIGH   (5)
    /*
     * Low Priority for SCI Server - must be higher than IPC echo test tasks
     * to prevent delay in handling Sciserver requests when test is performing
     * multicore ping/pong.
     */
    #define IPC_SETUP_SCISERVER_TASK_PRI_LOW    (4)
    /*Added*/
    /* ========================================================================== */
    /*                         Structure Declarations                             */
    /* ========================================================================== */
    
    /* None */
    
    /* ==========================================================================*/
    /*                          Function Declarations                             */
    /* ========================================================================== */
    
    static void CanApp_TaskFxn(void* a0, void* a1);
    static void CanApp_Shutdown(void);
    /*Added*/
    //sint32 SetupSciServer(void);
    static void taskFxn(void* a0, void* a1);
    void CanProfile_setupSciServer(void);
    void ipc_initSciclient(void);
    void Ipc_setupSciServer(void* a0, void* a1);
    /*Added*/
    /* ========================================================================== */
    /*                            Global Variables                                */
    /* ========================================================================== */
    /* application stack */
    static uint8 CanApp_TaskStack[APP_TASK_STACK] __attribute__((aligned(32)));
    /*Added */
    static uint8_t  gAppTskStackMain[APP_TSK_STACK_MAIN] __attribute__ ((aligned(8192)));
    static uint8_t  gSciserverInitTskStack[APP_SCISERVER_INIT_TSK_STACK] __attribute__ ((aligned(8192)));
    /*Added*/
    /**< Stack for the task */
    static canAppTaskObj_t  CanApp_TestPrms;
    /**< Test parameters */
    static HwiP_Handle      CanApp_IsrHndls[CAN_MAX_CONTROLLER];
    /**< Stores the ISR handles */
    extern SemaphoreP_Handle CanIf_TxConfirmationSemaphore;
    /**< TX Confirmation semaphore, would be posted when TX completes */
    extern SemaphoreP_Handle CanIf_RxConfirmationSemaphore;
    /**< Rx Confirmation semaphore, would be posted when TX completes */
    /* ========================================================================== */
    /*                            External Variables                              */
    /* ========================================================================== */
    extern uint32 CanIf_DrvStatus;
    /**< CAN IF Driver Status, defined in CanIf.c */
    
    /* ========================================================================== */
    /*                          Function Definitions                              */
    /* ========================================================================== */
    const Ipc_ResourceTable ti_ipc_remoteproc_ResourceTable __attribute__ ((section (".resource_table"), aligned (4096))) = 
    {
        {
            1U,                   /* we're the first version that implements this */
            2U,         /* number of entries in the table */
            {
                0U, 
                0U,                /* reserved, must be zero */
            }
        },
    };
    int main(void)
    {
        TaskP_Handle task;
        TaskP_Params taskParams;
       
    
    
        /* Relocate FreeRTOS Reset Vectors from BTCM*/
        void _freertosresetvectors (void);  
        memcpy((void *)0x0, (void *)_freertosresetvectors, 0x40);
    
        OS_init();
        /* Initialize the task params */
        TaskP_Params_init(&taskParams);
        /* Set the task priority higher than the default priority (1) */
        taskParams.priority = 2;
        taskParams.stack        = gAppTskStackMain;
        taskParams.stacksize    = sizeof (gAppTskStackMain);
    
        task = TaskP_create(taskFxn, &taskParams);
        if(NULL == task)
        {
            OS_stop();
        }
        OS_start();    /* does not return */
    
    }
    static void taskFxn(void* a0, void* a1)
    {
         //sint32 ret = CSL_PASS;
    #ifdef UART_ENABLED
        AppUtils_Init();
    #endif
        /* Initialize SCI Client - It must be called before board init */
        ipc_initSciclient();
    
        TaskP_Handle sciserverInitTask;
        TaskP_Params sciserverInitTaskParams;
        /* Initialize SCI Client Server */
            //ret = SetupSciServer();
        //if(ret != CSL_PASS)
         TaskP_Params_init(&sciserverInitTaskParams);
         sciserverInitTaskParams.priority     = IPC_INIT_SCISERVER_TASK_PRI;
         sciserverInitTaskParams.stack        = gSciserverInitTskStack;
        sciserverInitTaskParams.stacksize    = sizeof (gSciserverInitTskStack);
    
        sciserverInitTask = TaskP_create(Ipc_setupSciServer, &sciserverInitTaskParams);
        if(NULL == sciserverInitTask)
         {
            OS_stop();
         }
        CanApp_Startup();
        CanApp_PowerAndClkSrc();
    
        /* Initialize dummy CAN IF */
        CanIf_Init(NULL);
         TaskP_Handle task;
         TaskP_Params taskParams;
    
        if (CANIF_DRV_INITIALIZED == CanIf_DrvStatus)
        {
            /* Initialize the task params */
            TaskP_Params_init(&taskParams);
            //taskParams.instance->name = CAN_PROFILE_DEMO_TASK_NAME;
            /* Set the task priority higher than the default priority (1) */
            taskParams.priority     = 4;
            taskParams.stack        = CanApp_TaskStack;
            taskParams.stacksize    = sizeof (CanApp_TaskStack);
    
            task = TaskP_create(&CanApp_TaskFxn, &taskParams);
            if(NULL == task)
            {
                OS_stop();
            }
            //OS_start();    /* does not return */
        }
        else
        {
            AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
                    " Error : CAN IF not initialized !!!\n");
        }
    
        //return(0);
    }
    void ipc_initSciclient(void)
    {
        int32_t ret = CSL_PASS;
        Sciclient_ConfigPrms_t        config;
    
        /* Now reinitialize it as default parameter */
        ret = Sciclient_configPrmsInit(&config);
        if (ret != CSL_PASS)
        {
            AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "Sciclient_configPrmsInit Failed\n");
        }
    
    #if (defined (BUILD_MCU1_0) && (defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J721S2)))
        if (ret == CSL_PASS)
        {
            ret = Sciclient_boardCfgParseHeader(
                (uint8_t *)SCISERVER_COMMON_X509_HEADER_ADDR,
                &config.inPmPrms, &config.inRmPrms);
            if (ret != CSL_PASS)
            {
                AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "Sciclient_boardCfgParseHeader Failed\n");
            }
        }
    #endif
    
        //return(0);
        if (ret == CSL_PASS)
        {
            ret = Sciclient_init(&config);
            if (ret != CSL_PASS)
            {
                AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "Sciclient_init Failed\n");
            }
        }
    
        /* DEBUG: Print PLL/Clock related info to compare before/after Linux boots */
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "ipc_initSciclient done\n");
    }
    
    void Ipc_setupSciServer(void* a0, void* a1)
    {
    
        Sciserver_TirtosCfgPrms_t appPrms;
        int32_t ret = CSL_PASS;
        char *version_str = NULL;
        char *rmpmhal_version_str = NULL;
    
        ret = Sciserver_tirtosInitPrms_Init(&appPrms);
    
        appPrms.taskPriority[SCISERVER_TASK_USER_LO] =
                                                IPC_SETUP_SCISERVER_TASK_PRI_LOW;
        appPrms.taskPriority[SCISERVER_TASK_USER_HI] =
                                                IPC_SETUP_SCISERVER_TASK_PRI_HIGH;
    
        if (ret == CSL_PASS)
        {
            ret = Sciserver_tirtosInit(&appPrms);
        }
    
        version_str = Sciserver_getVersionStr();
        rmpmhal_version_str = Sciserver_getRmPmHalVersionStr();
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "DM Built On: %s %s\n", __DATE__, __TIME__);
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "Sciserver Version: %s\n", version_str);
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "RM_PM_HAL Version: %s\n", rmpmhal_version_str);
    
        if (ret == CSL_PASS)
        {
            AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "Starting Sciserver..... PASSED\n");
        }
        else
        {
            AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "Starting Sciserver..... FAILED\n");
        }
    
        return;
    }
    static void CanApp_TaskFxn(void* a0, void* a1)
    {
        CanApp_PlatformInit();
        Utils_prfInit();
    
        Utils_prfLoadRegister (TaskP_self(), CAN_PROFILE_DEMO_TASK_NAME);
    
        CanApp_TestPrms.numTxPackets = APP_NUM_MSG_PER_ITERATION;
        CanApp_TestPrms.numIterations = APP_NUM_ITERATION;
    
        TaskP_yield();
    
        CanApp_ProfileTest(&CanApp_TestPrms);
    
        can_set_control_mode_v();
        TaskP_sleep(100);
    
        // while (1)
        // {
            // can_send_data();
            //AppUtils_delay(1000);
            // TaskP_sleep(100);
    
            // process_received_can_message();
        // }
            
    
        CanApp_Shutdown();
    
        Utils_prfLoadUnRegister (TaskP_self());
        Utils_prfDeInit();
        return;
    }
    
    /** \brief Application tear down functions */
    static void CanApp_Shutdown(void)
    {
        uint32 idx;
    
        for (idx = 0U; idx < CAN_MAX_CONTROLLER; idx++)
        {
            if (NULL != CanApp_IsrHndls[idx])
            {
                if (HwiP_OK != HwiP_delete(CanApp_IsrHndls[idx]))
                {
                    AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
                                    " Error!!! Could not De register"
                                    " the ISR for instance %d!!!\n", idx);
                    break;
                }
            }
        }
    
        if (NULL != CanIf_TxConfirmationSemaphore)
        {
            SemaphoreP_delete(CanIf_TxConfirmationSemaphore);
            if (NULL != CanIf_RxConfirmationSemaphore)
            {
                SemaphoreP_delete(CanIf_RxConfirmationSemaphore);
            }
        }
        return;
    }
    
    sint32 SetupSciServer(void)
    {
    
       sint32 ret = CSL_PASS;
    #if (defined (BUILD_MCU1_0) && (defined (SOC_J721E) || defined (SOC_J7200)))
        Sciserver_TirtosCfgPrms_t appPrms;
        Sciclient_ConfigPrms_t clientPrms;
    
       appPrms.taskPriority[SCISERVER_TASK_USER_LO] = 1;
        appPrms.taskPriority[SCISERVER_TASK_USER_HI] = 4;
    
        /* Sciclient needs to be initialized before Sciserver. Sciserver depends on
         * Sciclient API to execute message forwarding */
        ret = Sciclient_configPrmsInit(&clientPrms);
        if (ret == CSL_PASS)
        {
            ret = Sciclient_init(&clientPrms);
        }
    
        if (ret == CSL_PASS)
        {
            ret = Sciserver_tirtosInit(&appPrms);
        }
    
        if (ret == CSL_PASS)
        {
            AppUtils_Printf(MSG_NORMAL, "Starting Sciserver..... PASSED\n");
        }
        else
        {
            AppUtils_Printf(MSG_NORMAL, "Starting Sciserver..... FAILED\n");
        }
    
    #endif
        return ret;
    }
    

    /*==========================*/
    /*     Linker Settings      */
    /*==========================*/

    --retain="*(.bootCode)"
    --retain="*(.startupCode)"
    --retain="*(.startupData)"
    --retain="*(.irqStack)"
    --retain="*(.fiqStack)"
    --retain="*(.abortStack)"
    --retain="*(.undStack)"
    --retain="*(.svcStack)"
    --retain="*(.resource_table)"

    --fill_value=0
    --stack_size=0x4000
    --heap_size=0x8000
    --entry_point=_freertosresetvectors

    -stack  0x4000  /* SOFTWARE STACK SIZE */
    -heap   0x8000  /* HEAP AREA SIZE      */

    /*-------------------------------------------*/
    /*       Stack Sizes for various modes       */
    /*-------------------------------------------*/
    __IRQ_STACK_SIZE   = 0x1000;
    __FIQ_STACK_SIZE   = 0x0100;
    __ABORT_STACK_SIZE = 0x0100;
    __UND_STACK_SIZE   = 0x0100;
    __SVC_STACK_SIZE   = 0x0100;

    /*--------------------------------------------------------------------------*/
    /*                               Memory Map                                 */
    /*--------------------------------------------------------------------------*/
    --define FILL_PATTERN=0xFEAA55EF
    --define FILL_LENGTH=0x100
    MEMORY
    {
        MCU_R5F_TCMA_VECS       (X) : ORIGIN = 0x00000000 LENGTH = 0x00000040
        MCU_R5F_TCMA            (X) : ORIGIN = 0x00000040 LENGTH = 0x00007FC0
        MCU_R5F_TCMB_VECS       (X) : ORIGIN = 0x41010000 LENGTH = 0x00000040
        MCU_R5F_TCMB            (X) : ORIGIN = 0x41010040 LENGTH = 0x00007FC0

        /*==================== MCU0_R5F_1 SoC View =========================*/
        MCU0_R5F1_ATCM (RWIX)       : ORIGIN = 0x41400000 LENGTH = 0x00008000
        MCU0_R5F1_BTCM (RWIX)       : ORIGIN = 0x41410000 LENGTH = 0x00008000

        /*========================J721E MCMS3 LOCATIONS ===================*/
        /*---------- J721E Reserved Memory for ARM Trusted Firmware -------*/
        MSMC3_ARM_FW  (RWIX)        : ORIGIN = 0x70000000 LENGTH = 0x00040000   /* 256KB       */
        MSMC3         (RWIX)        : ORIGIN = 0x70040000 LENGTH = 0x007B0000   /* 8MB - 320KB */
        /*------------- J721E Reserved Memory for DMSC Firmware -----------*/
        MSMC3_DMSC_FW (RWIX)        : ORIGIN = 0x707F0000 LENGTH = 0x00010000   /* 64KB        */

     /*   DDR0    (RWIX)          : origin=0x80000000 length=0x8000000      /* 2GB */

        /* Used in this file */
      /*  DDR0_MCU_1_0 (RWIX)     : origin=0x97000000 length=0x1000000       /* 16MB */
      /*   DDR0_MCU_1_0_RSC_TBL (RWIX) : origin=0xA0100000 length=0x100000       /* 1MB */
         DDR0_MCU_1_0_RSC_TBL (RWIX) : origin=0xA0100000 length=0x00000400
    /*   DDR0_MCU_1_0 (RWIX)     : origin=0xA0200000 length=0xE00000       /* 14MB */
         DDR0_MCU_1_0 (RWIX)     : origin=0xA0100400 length=0xE00000       /* 14MB */


        /* Refer the user guide for details on persistence of these sections */
        OCMC_RAM_SBL_RUNTIME (RWIX) : origin=0x41C00000 length=0x80000
        OCMC_RAM_BOARD_CFG (RWIX)   : origin=0x41C80000 length=0x2000
        OCMC_RAM (RWIX)             : origin=0x41C82000 length=0x7DB00
        OCMC_RAM_X509_HEADER (RWIX) : origin=0x41CFFB00 length=0x500


    }  /* end of MEMORY */

    /*----------------------------------------------------------------------------*/
    /* Section Configuration                                                      */

    SECTIONS
    {
       .freertosrstvectors : {} palign(8)   > MCU_R5F_TCMB_VECS
        .bootCode        : {} palign(8)      > MCU_R5F_TCMB
        .startupCode     : {} palign(8)      > MCU_R5F_TCMB
        .startupData     : {} palign(8)      > MCU_R5F_TCMB, type = NOINIT
        GROUP {
            .text.hwi    : palign(8)
            .text.cache  : palign(8)
            .text.mpu    : palign(8)
            .text.boot   : palign(8)
        }                           > MCU_R5F_TCMB
        .text        : {} palign(8)         > DDR0_MCU_1_0
        .const       : {} palign(8)         > DDR0_MCU_1_0
        .rodata     : {} palign(8)          > DDR0_MCU_1_0
        .cinit       : {} palign(8)         > DDR0_MCU_1_0
        .pinit       : {} palign(8)         > DDR0_MCU_1_0
        .bss         : {} align(4)          > DDR0_MCU_1_0
        .far         : {} align(4)          > DDR0_MCU_1_0
        .data        : {} palign(128)     > DDR0_MCU_1_0
        .data_buffer: {} palign(128)     > DDR0_MCU_1_0
        .sysmem      : {}             > DDR0_MCU_1_0
        .stack      : {} align(4)        > DDR0_MCU_1_0 (HIGH) fill=FILL_PATTERN
    /*    .bss.devgroup*  : {} align(4)       > DDR0_MCU_1_0
        .const.devgroup*: {} align(4)       > DDR0_MCU_1_0*/
        .data_user      : {} align(4)       > DDR0_MCU_1_0
        .boardcfg_data  : {} align(4)       > DDR0_MCU_1_0

        .resource_table : 
        {
            __RESOURCE_TABLE = .;
        }                                   > DDR0_MCU_1_0_RSC_TBL
       
        /* USB or any other LLD buffer for benchmarking */
        .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0_MCU_1_0

        .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > DDR0_MCU_1_0(HIGH)
        RUN_START(__IRQ_STACK_START)
        RUN_END(__IRQ_STACK_END)

        .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > DDR0_MCU_1_0(HIGH)
        RUN_START(__FIQ_STACK_START)
        RUN_END(__FIQ_STACK_END)

        .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > DDR0_MCU_1_0(HIGH)
        RUN_START(__ABORT_STACK_START)
        RUN_END(__ABORT_STACK_END)

        .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > DDR0_MCU_1_0(HIGH)
        RUN_START(__UND_STACK_START)
        RUN_END(__UND_STACK_END)

        .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > DDR0_MCU_1_0(HIGH)
        RUN_START(__SVC_STACK_START)
        RUN_END(__SVC_STACK_END)

        /* Additional sections settings     */
        McalTextSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_1_0
        {
            .=align(4);
            __linker_spi_text_start = .;
            . += FILL_LENGTH;
            *(SPI_TEXT_SECTION)
            *(SPI_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_text_end = .;

            .=align(4);
            __linker_gpt_text_start = .;
            . += FILL_LENGTH;
            *(GPT_TEXT_SECTION)
            *(GPT_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_text_end = .;

            .=align(4);
            __linker_dio_text_start = .;
            . += FILL_LENGTH;
            *(DIO_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_text_end = .;

            .=align(4);
            __linker_eth_text_start = .;
            . += FILL_LENGTH;
            *(ETH_TEXT_SECTION)
            *(ETH_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_text_end = .;

            .=align(4);
            __linker_ethtrcv_text_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_text_end = .;

            .=align(4);
            __linker_can_text_start = .;
            . += FILL_LENGTH;
            *(CAN_TEXT_SECTION)
            *(CAN_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_text_end = .;

            .=align(4);
            __linker_wdg_text_start = .;
            . += FILL_LENGTH;
            *(WDG_TEXT_SECTION)
            *(WDG_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_text_end = .;

            .=align(4);
            __linker_pwm_text_start = .;
            . += FILL_LENGTH;
            *(PWM_TEXT_SECTION)
            *(PWM_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_text_end = .;

            __linker_adc_text_start = .;
            . += FILL_LENGTH;
            *(ADC_TEXT_SECTION)
            *(ADC_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_text_end = .;

            .=align(4);
            __linker_cdd_ipc_text_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_TEXT_SECTION)
            *(CDD_IPC_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_text_end = .;

        }
        McalConstSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_1_0
        {
            .=align(4);
            __linker_spi_const_start = .;
            . += FILL_LENGTH;
            *(SPI_CONST_32_SECTION)
            *(SPI_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_const_end = .;

            .=align(4);
            __linker_gpt_const_start = .;
            . += FILL_LENGTH;
            *(GPT_CONST_32_SECTION)
            *(GPT_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_const_end = .;

            .=align(4);
            __linker_dio_const_start = .;
            . += FILL_LENGTH;
            *(DIO_CONST_32_SECTION)
            *(DIO_CONST_UNSPECIFIED_SECTION)
            *(DIO_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_const_end = .;

            .=align(4);
            __linker_can_const_start = .;
            . += FILL_LENGTH;
            *(CAN_CONST_8_SECTION)
            *(CAN_CONST_32_SECTION)
            *(CAN_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_const_end = .;

            .=align(4);
            __linker_eth_const_start = .;
            . += FILL_LENGTH;
            *(ETH_CONST_32_SECTION)
            *(ETH_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_const_end = .;

            .=align(4);
            __linker_ethtrcv_const_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_CONST_32_SECTION)
            *(ETHTRCV_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_const_end = .;

            .=align(4);
            __linker_wdg_const_start = .;
            . += FILL_LENGTH;
            *(WDG_CONST_32_SECTION)
            *(WDG_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_const_end = .;

            .=align(4);
            __linker_pwm_const_start = .;
            . += FILL_LENGTH;
            *(PWM_CONST_32_SECTION)
            *(PWM_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_const_end = .;

            .=align(4);
            __linker_adc_const_start = .;
            . += FILL_LENGTH;
            *(ADC_CONST_32_SECTION)
            *(ADC_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_const_end = .;

            .=align(4);
            __linker_cdd_ipc_const_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_CONST_32_SECTION)
            *(CDD_IPC_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_const_end = .;
        }

        McalInitSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_1_0
        {
            .=align(4);
            __linker_spi_init_start = .;
            . += FILL_LENGTH;
            *(SPI_DATA_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_init_end = .;

            .=align(4);
            __linker_gpt_init_start = .;
            . += FILL_LENGTH;
            *(GPT_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_init_end = .;

            .=align(4);
            __linker_pwm_init_start = .;
            . += FILL_LENGTH;
            *(PWM_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_init_end = .;

            .=align(4);
            __linker_dio_init_start = .;
            . += FILL_LENGTH;
            *(DIO_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_init_end = .;

            .=align(4);
            __linker_eth_init_start = .;
            . += FILL_LENGTH;
            *(ETH_DATA_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_init_end = .;

            .=align(4);
            __linker_ethtrcv_init_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_DATA_INIT_UNSPECIFIED_SECTION)
            *(ETHTRCV_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_init_end = .;

            .=align(4);
            __linker_can_init_start = .;
            . += FILL_LENGTH;
            *(CAN_DATA_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_init_end = .;

            .=align(4);
            __linker_wdg_init_start = .;
            . += FILL_LENGTH;
            *(WDG_DATA_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_init_end = .;

            .=align(4);
            __linker_adc_init_start = .;
            . += FILL_LENGTH;
            *(ADC_DATA_INIT_UNSPECIFIED_SECTION)
            *(ADC_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_init_end = .;

            .=align(4);
            __linker_cdd_ipc_init_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_DATA_INIT_UNSPECIFIED_SECTION)
            *(CDD_IPC_DATA_INIT_32_SECTION)
            *(CDD_IPC_DATA_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_init_end = .;
        }
        McalNoInitSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_1_0, type = NOINIT
        {
            .=align(4);
            __linker_spi_no_init_start = .;
            . += FILL_LENGTH;
            *(SPI_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_no_init_end = .;

            .=align(4);
            __linker_gpt_no_init_start = .;
            . += FILL_LENGTH;
            *(GPT_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_no_init_end = .;

            .=align(4);
            __linker_dio_no_init_start = .;
            . += FILL_LENGTH;
            *(DIO_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_no_init_end = .;

            .=align(4);
            __linker_eth_no_init_start = .;
            . += FILL_LENGTH;
            *(ETH_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_no_init_end = .;

            .=align(4);
            __linker_ethtrcv_no_init_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_DATA_NO_INIT_UNSPECIFIED_SECTION)
            *(ETHTRCV_DATA_NO_INIT_16_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_no_init_end = .;

            .=align(4);
            __linker_can_no_init_start = .;
            . += FILL_LENGTH;
            *(CAN_DATA_NO_INIT_UNSPECIFIED_SECTION)
            *(CAN_DATA_NO_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_no_init_end = .;

            .=align(4);
            __linker_wdg_no_init_start = .;
            . += FILL_LENGTH;
            *(WDG_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_no_init_end = .;

            .=align(4);
            __linker_pwm_no_init_start = .;
            . += FILL_LENGTH;
            *(PWM_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_no_init_end = .;

            __linker_adc_no_init_start = .;
            . += FILL_LENGTH;
            *(ADC_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_no_init_end = .;

            __linker_cdd_ipc_no_init_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_DATA_NO_INIT_UNSPECIFIED_SECTION)
            *(CDD_IPC_DATA_NO_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_no_init_end = .;

        }
        /* Example Utility specifics */
        VariablesAlignedNoInitSection : align=8, load > DDR0_MCU_1_0, type = NOINIT
        {
            .=align(8);
            __linker_cdd_ipc_no_init_align_8b_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_DATA_NO_INIT_8_ALIGN_8B_SECTION)
            .=align(8);
            . += FILL_LENGTH;
            __linker_cdd_ipc_no_init_align_8b_end = .;
        }
        /* Example Utility specifics */
        UtilityNoInitSection : align=4, load > DDR0_MCU_1_0, type = NOINIT
        {
            .=align(4);
            __linker_utility_no_init_start = .;
            . += FILL_LENGTH;
            *(EG_TEST_RESULT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_utility_no_init_end = .;
        }
        SciClientBoardCfgSection : align=128, load > DDR0_MCU_1_0, type = NOINIT
        {
            .=align(128);
            __linker_boardcfg_data_start = .;
            . += FILL_LENGTH;
            *(.boardcfg_data)
            .=align(128);
            . += FILL_LENGTH;
            __linker_boardcfg_data_end = .;
        }
        /* This section is used for descs and ring mems. It's best to have
         * it in OCMRAM or OCMC_RAM_SCISERVER */
        McalUdmaSection : fill=FILL_PATTERN, align=128, load > DDR0_MCU_1_0
        {
            .=align(128);
            __linker_eth_udma_start = .;
            . += FILL_LENGTH;
            *(ETH_UDMA_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_udma_end = .;
        }
        McalTxDataSection : fill=FILL_PATTERN, align=128, load > DDR0_MCU_1_0, type = NOINIT
        {
            .=align(128);
            __linker_eth_tx_data_start = .;
            . += FILL_LENGTH;
            *(ETH_TX_DATA_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_tx_data_end = .;
        }
        McalRxDataSection : fill=FILL_PATTERN, align=128, load > DDR0_MCU_1_0, type = NOINIT
        {
            .=align(128);
            __linker_eth_rx_data_start = .;
            . += FILL_LENGTH;
            *(ETH_RX_DATA_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_rx_data_end = .;
        }
    }  /* end of SECTIONS */

    /*----------------------------------------------------------------------------*/
    /* Misc linker settings                                                       */


    /*-------------------------------- END ---------------------------------------*/

    Regards,

    M Indumathi

  • Hi Indumathi,

    Will need a day or two more to do some more experiments, but so far, I think the issue is that vision_apps expects its own MCU1_0 firmware which the modifications to the MCU1_0 firmware by following the FAQ has a conflict with. MCU1_0 is a bit special in the sense that it runs some extra software that the system has a dependency on (i.e.: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j721s2/11_02_01_03/exports/docs/psdk_rtos/docs/user_guide/developer_notes_mcu1_0_sysfw.html). 

    So the IPC error is most likely coming from such conflict, as the FAQ is built on old SDK version of 8.2 while the code base is on 11.2, which is a couple years apart.

    Otherwise, you would need an additional change to the Linux DTS file such that the CAN interface used by RTOS is not used by Linux, to avoid resource conflict.

    Regards,

    Takuma