AM6421: AM64 Power Sequence and USB data lines

Hello Joe,

In the AM64x datasheet, in section 6.11.2.2.1 Power-Up Sequencing it is defined the ordered waveform power-up sequence. All power supplies must be stable for a minimum of 9.5ms before MCU_PORz is deasserted (released high).

From a pure power supply sequence standpoint, your ordering correctly mirrors the AM64x prescribed sequence. The 3.3V supply, which includes VDDA_3P3_USB0, is indeed the first supply to ramp, so the TPD8S600A enabling D+/D- at that point is aligned with the datasheet sequence. The AM64x USB design guide confirms that the VBUS pin must be connected through a voltage divider + zener clamp, which you have, connecting 3.3V permanently to the VBUS pin is not allowed. Your zener protection approach is consistent with the recommendation.

Joe Paolino said:

Should D+/D- attachment be delayed until some time after reset release?

TI does not explicitly prohibit D+/D- being present before reset release, and here is the relevant reasoning:

• VDDA_3P3_USB0 (3.3V) is the very first supply in the power-on sequence, it is intended to be present throughout. The USB2 PHY's ESD and analog circuitry rely on VDDA_3P3_USB0 being up early.
• In the AM64x hardware design guide in section 6.1.1.1.4 Peripheral Analog Power Supply Checklist is stated:

"When USB driver is not initialized and the USB calibration procedure does not happen, connecting the supplies and leaving all of the USB pins for USB0 is acceptable."

This implies the D+/D- pins being passively present (no active driving) during power-up is not a concern.

• The USB2 PHY has integrated termination resistors (1.5 kΩ and 15 kΩ) and the AM64 keeps the USB controller internally reset (pwrup_rst_n = 0 by default) until software explicitly deasserts it, so the PHY is not actively driving or responding to D+/D- during power-up or immediately after reset release.
• The USB controller initialization is a software-driven sequence that happens well after reset release: configure SERDES → configure USB3P0SS_W1 → deassert PWRUP_RST_N → wait for ready. The D+/D- lines won't be actively negotiated until software has run through this sequence.

Please review the AM64x Errata document if your AM6421 is affected by errata i2409 USB2 PHY locks up due to short suspend.

Best Regards,

Borislav Lazarkov

Borislav, thank you for this detailed response.  We have in fact modified the USB driver for FreeRTOS to match the Linux driver which fixes i2409.  We have noticed connection reliability improvements as a result of this.  

There has also been some commenting on this forum about clock tree readiness which is managed by the DMSC/SysFW.  I'm updating the hardware design and was interested to know if could do anything there, such as delaying D+/D- attachment until well after clock tree stabilization, Cadence driver initialization, or any other race conditions.

Thank you,

Joe

Hello Joe,

That's great to hear that aligning the FreeRTOS USB driver with the Linux driver resolved the i2409 behavior.

After reset release (MCU_PORz deassertion), the DMSC ROM runs first, loads and authenticates SysFW into the M3 core, and only then does SysFW take ownership of PLL and clock tree configuration. Until that sequence completes (~19 ms after reset release), the USB2 PHY clocks, including MAIN_PLL2 sourcing the 960 MHz USB reference clock and the LPSC_USB0 clock gate, are not guaranteed stable. You can review the AM64x TRM section 5.2.1 Power Management Overview. The Cadence USB wrapper driver (cdns-usb3) then needs to complete its own initialization and deassertion of PWRUP_RST_N before the PHY is calibrated and ready to respond to D+/D- signaling . If a USB device presents a connect event before this sequence completes, the PHY may miss the attach event or enter its enumeration state machine in a partially initialized state, manifesting as intermittent non-detection on first boot that resolves on a re-plug.

Since you are using a TPD8S600A, you are well positioned to address this in hardware. The TPD8S600A has an active-low EN pin that controls the D+/D- pass-through path, which gives you a clean interception point. What you could do is route an AM64x GPIO to the TPD8S600A EN pin. Pull EN high (disabled) by default via a resistor to 3.3V, and assert it low in software only after the Cadence USB driver has completed initialization and PWRUP_RST_N has been deasserted in the USB wrapper. This ties D+/D- attachment precisely to driver readiness regardless of boot time variation and is the most robust approach.

Best Regards,

Borislav Lazarkov

Hi Borislav,

I might be misunderstanding.  The TPD8S300A does not have any enable line.  Is there a different component that you would recommend for this task?

Thanks

Joe

Hello Joe,

I apologies for the error in the previous response, I misled you. The TPD8S300A (and TPD8S600A) are passive ESD clamp arrays with no enable or switching function, so they cannot be used to gate the D+/D- path directly. The GPIO-controlled gating approach is still valid and recommended, but it requires either replacing the TPD8S300A with a device that integrates an enable pin, or adding a separate USB switch in series with the existing ESD clamp. There are 2 options:

• Option 1 — Single Chip Replacement: TPD4S014

The TPD4S014 is a USB charger port protection device that covers both VBUS OVP (up to 28V) and IEC 61000-4-2 ESD protection on D+/D-, and importantly includes an active-low EN pin that directly enables or disables the D+/D- data line path. This makes it a clean drop-in replacement architecture for the TPD8S300A in your design, you retain full ESD protection while gaining GPIO-controlled gating of the D+/D- path from the AM64x.

https://www.ti.com/product/TPD4S014

• Option 2 — Additive Approach: Keep TPD8S300A, Add TS3USB30E

If you would prefer to retain the TPD8S300A for ESD clamping and add the enable function separately, the TS3USB30E is a USB 2.0 Hi-Speed analog switch supporting 480 Mbps signaling on D+/D- with a GPIO-controlled enable pin. Placed in series between the TPD8S300A and the AM64x USB pins, this separates the ESD protection function from the signal gating function cleanly and avoids a full BOM respin.

https://www.ti.com/product/TS3USB30E

In both cases, the GPIO-controlled boot sequencing approach described previously remains valid, hold EN high (path disabled) by default via a pull-up to 3.3V, and assert it low from the AM64x GPIO only after the Cadence USB driver has completed initialization and PWRUP_RST_N has been deasserted. A ≥ 300 ms passive RC delay on EN remains an option as well if a no-software-change solution is preferred.

Best Regards,

Borislav Lazarkov

There appears to be a significant number of issues with this response.  I must assume these were AI assisted responses.

• The TPD8S600A does not exist
• The TPD8S300A does have protective overvoltage gating on D+/D-, but activated with VPWR 
• The TPD4S014 protects VBUS with an overvoltage gate, but only provides ESD protection to D+/D-

Thank you for the response, Borislav.  My typo above certainly did not help the confusion.