Hi all,
We measured that the SYSCLK4 is not very stable when the DSP runs at 1.2GHZ and the temperature of the DSP rises. I can add that we use a DIV4 value of 0x3 that is to say 150Mhz The results are better when we set a DIV value of 0x7(SYSCLK4 = 75MHz).
According to the the errata of the C6455 we should not use SYSCLK4 to clock the EMIFA bus, it might be related to this bug? Actually no additional information are present about this bug in the datasheet.
Is there any known issue about this clock?