AM6442: AM6442 VBUS logic level

Hello Thierry,

The USB0_VBUS pin on the SoC is not a raw 5 V input. It is an analog sense pin whose internal USB PHY comparators detect three OTG threshold events:

These thresholds come from the USB 2.0 / OTG specification, and the SoC's internal PHY evaluates them at the USB0_VBUS pin after the voltage has been scaled down.

The recommended divider (16.5 kΩ + 3.48 kΩ, +/-1% tolerance) with a 6.8 V Zener clamp, which is shown in the AM64x Datasheet in section 8.2.4 USB VBUS Design Guidelines, produces the following scaled voltages at the USB0_VBUS pin for a 5 V VBUS:

V_pin = V_VBUS × [3.48k / (16.5k + 3.48k)]

       = 5 V × [3.48 / 19.98]

       ≈ 5 V × 0.1742

       ≈ 0.871 V → nominal ~1.65 V

The nominal input voltage applied to USB0_VBUS equals the resistor divider output when VBUS = 5 V. TI's recommended values give approximately ~1.65 V nominal at the pin when VBUS = 5 V.

The Recommended Operating Conditions define:

• USB0_VBUS min = 0 V
• USB0_VBUS max = 3.465 V (≈ VDDA_3P3_USB0 max)
• Absolute maximum = 3.6 V

To replicate the resistor divider behavior with an external comparator driving USB0_VBUS, you need to mimic what the scaled voltage looks like at the pin for each OTG state.

If you are using a comparator instead:

• The comparator output must be a switched signal, not a permanent rail. Connecting a permanent supply (e.g., always-on 1.65 V) to USB0_VBUS is explicitly prohibited, it must be switchable to 0 V at end-of-session.
• Maximum voltage at USB0_VBUS pin = 3.465 V (Recommended Operating Condition), absolute max = 3.6 V.
• For USB Type-C: The USB Type-C companion/PD controller handles DRD role switching via the CC pins. The CC pins at the connector must be independently pulled down to GND via 5.1 kΩ resistors (for device mode). The USB0_VBUS sense path is still needed to indicate session valid/end to the SoC.
• The comparator output levels driving USB0_VBUS should represent:
  • HIGH (~1.65 V or up to ~3.3 V) → VBUS present / session valid
  • LOW (0 V) → No session / VBUS absent

Best Regards,

Borislav Lazarkov

Hello, 

As far as I understand, I don't find the same bridge : 

USBn_VBUS= ~10K/(30K) x VBUS.
So for 5V=> USBn_VBUS= 1.66V
Does it implies that 3.465V>voltages >1.66V allow to detect that VBUS is present/session valid?

Hello Thierry,

Thank you for the detailed feedback, your understanding is correct!

Your formula USBn_VBUS = ~10k / (10k + 16.5k + 3.48k) × VBUS ≈ 1.66 V at 5 V is right and matches what is documented in the AM64x TRM in section 12.2.4.2.3 VBUS Sense.

However, to answer your question more precisely, the valid detection window is not strictly "> 1.66 V". The 1.66 V is only the nominal scaled value when VBUS = 5 V. The actual thresholds to keep in mind are:

So if you replace the resistor bridge with an external comparator, the target logic levels at the USBn_VBUS SoC pin should be:

• LOW = 0 V → No VBUS / session ended
• HIGH = ~1.65 V to 3.3 V (must stay below 3.465 V max) → VBUS present / session valid

One critical design rule to keep in mind from the Schematic Design Guidelines and Schematic Review Checklist for AM6442, AM6422, AM6412 and AM2434 (ALV) Processor Families in section 7.4.2 Universal Serial Bus (USB2.0): the comparator output driving USBn_VBUS must be switchable to 0 V at end-of-session. Connecting a permanently-driven HIGH voltage, even at 1.65 V, to USBn_VBUS is explicitly not allowed per TI guidelines.

Best Regards,

Borislav Lazarkov