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Interrupt Delay and Jitter with C5504

Howard Wang
Prodigy 235 points

Environment: Using C5504/150MHz and CCS 3.3

1. Interrupt Delay

Description:With INT1 connected to GPIO from FPGA pin and enable/config INT1 as an interrupt pin. Whenever INT1 triggered, first line in the service routine is to set GPIO8 and reset it as last line in the ISR routine. Connecting both IOs (INT1 and GPIO8) to oscilloscope, there are about 750ns delay between INT1 pulse (falling edge) and GPIO8 pulse (rising edge). With a special test, all other interrupts are disabled. The result is same.

Question: my understanding is that there are only 3 CPU cycles are needed to confirm the interrupt and register it. CPU cycle is about 7ns with 150 Mhz system clock. Even make it 10 times slow, 30 CPU cycles, it shall be 210ns. How could the delay be 750ns long?

2. INT1 ISR Jitter (+/- 1us) with timer enabled

Description: With 1ms timer (Timer2) enabled, GPIO8 pulse shows +/- 1us jitter from above test. Even in timer ISR, do nothing and return. The jitter (1us)  is always there. What could be a reason to cause this?

Please advice.

Thanks,

Howard

  • 0
    TI__Genius 14965 points

    Hi,

    1. Interrupt Delay: There are some latency on interrupt service. If you can disassemble your ISR code, you'll see them. Also GPIO access takes more than 1 cycles.

    2. I think that when the interrupt happens there could be in different states. For example, main code does nothing but waiting. When timer interrupt happens, it does "nop" operation, branch, or condition checking. It depends on what operation CPU doing. This can cause a Jitter .

       while (1) {

    asm("  nop");

      }

    Regards,

    Hyun

  • 0 in reply to Hyun Kim
    Prodigy 235 points

    Hi Hyun,

    For case 1, there are more than 750ns delay. With 150Mhz clock, there are more than 100 cycles. GPIO access delay could be ignored. There are lots of push and pop at beginning and end of ISR for sure. Is that possible the latency of interrupt service take more than 100 cycles?

    For case 2, This is related with case 1. The delay between hardware interrupt signal and GPIO triggered within ISR is 750ns with the jitter +/- 1us. It happens with timer interrupt enabled regardless what main was doing.  The Timer ISR is 1ms and interrupt reentry is enabled. This could be related with latency of ISR handling and would like to know about DSP design on related with this topic.

    Thanks,

    Howard