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C6747 shared RAM and L2 memory with cache enabled

scoutu75
Intellectual 440 points

Hello,

I'm optimizing the operation of my application running on a C6747 @ 375 MHz.  Also, I have configured L1P full cache, L1D full cache and L2 64 kB cache / 192 kB RAM.

I placed the .const section in the internal shared RAM (128 kB space) as opposed to the external SDRAM on EMIFB @ 125 MHz. I was thinking that it was quicker for the DSP core to access the shared RAM and cache the contents instead of accessing the external SDRAM and cache the contents.The system interconnect block in section 3.2 of SPRUFK4D shows that the path to EMIFB has an additional Switched Central Resource (SRC) and then a 32-bit bus instead of 64 bits for shared RAM.

After testing, it seems to be the opposite, the overall performance of my application is faster when .const data is in SDRAM. Would this be because shared RAM contents are not cached in L2 and/or L1. I went through the datasheets and the cache user guide but I cannot find information on shared RAM vs. cache. How can this behaviour be explained?

Thanks,

SC

  • 0
    TI__Guru* 84110 points

    SC,

    The Megamodule Reference Guide is where you can learn about how the DSP handles caching of memory elements outside of the Megamodule.

    Section 4.4.4 lists the entire set of MAR registers. The region of memory for the Shared RAM may be cached or not depending on your setting of the bit for that address range. The same is true for the SDRAM space; it is cached or not depending on the MAR setting.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

  • 0 in reply to RandyP
    Intellectual 440 points

    Hi Randy,

    I did set SDRAM to cacheable but did not think that the Shared RAM memory was set to non-cacheable by default. Now setting MAR[128] makes the application run as expected.

    When all relevant datasheets will be merged into a single document, searching for answers will be easier :)  (I think this is in progress but not with the C6747)

    Best regards,

    SC