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AM625: eMMC DDR52 mode

Tony Tang
Mastermind 30837 points

Part Number: AM625

DDR52 mode is removed since SDK10.1.  The customer used DDR52 mode in UBOOT with SDK9.2.1.9 as HS200 is not stable at that time. shipped quite a lot of pcs and haven't issue. 

The tested timing, it meet eMMC requirements also. 

Questions:

#1. Why remove DDR52 mode from datasheet and SDK?

#2. Is it due to other customer reported DDR52 mode stable issue then removed it?

#3. Did TI verify DDR52 mode?

Hope it is just not tested then removed it, customer need detail clarifiction if it is not supported, then proceed modification, that is not expected. 

  • 0
    TI__Guru 64995 points

    High Speed DDR mode was only included in the Advance Information datasheet. It was removed before publishing the first revision of the Production datasheet. 

    High Speed DDR data transfer mode was removed because the TI design team was not able to close timing with enough margin.

    After AM62x, the PHY used for MMCSD0 was updated to include additional delay options via the OTAPDLYSEL register field, which was increased from 4 bits of control to 5 bits of control. You can see this update implemented in the AM62Ax devices, which is able to support High Speed DDR.

    Regards,
    Paul

  • 0 in reply to peaves
    TI__Mastermind 30837 points
    peaves said:
    was not able to close timing with enough margin.

    Can I understand:  It meets timing requirements, just margin is not enough.

    Can we get detail data about the margin from timing closure team, help customer evaluate the risk of field deployed product, usually TI reserve excessive margin.

  • 0 in reply to Tony Tang
    TI__Guru 64995 points

    The design team was not able to close timing. They tried their best, but everything they tried resulted in negative margin. This is why additional delay was added to the next revision of the PHY. Therefore, it is not possible to support the High Speed DDR transfer mode on any AM62x device.

    Regards,
    Paul

  • 0 in reply to peaves
    TI__Mastermind 30837 points

    In latest SDK12.1, AM62A dts; ti,otap-del-sel-ddr52 = <0x15>;  4bit OTAPDLYSEL is enough.

    in  SDK 8.3 AM62x dts:     ti,otap-del-sel-ddr52 = <0x9>;

    in AM62x SDK9.2.:    ti,otap-del-sel-ddr52 = <0x5>;

    Since eMMC DDR mode is not supported from start, why software team keep on modify the otap delay value across SDK8.3 to SDK9.2 for AM62x, the value is much less than 15.. Is it a arbitrary change, or try to bring up DDR mode.

    Although AM62A has 5bit OTAPDLYSEL field, 4bit is enough to hold 15.

  • 0 in reply to Tony Tang
    TI__Guru**** 182156 points

    Hi Tony,

    Tony Tang said:
    In latest SDK12.1, AM62A dts; ti,otap-del-sel-ddr52 = <0x15>;  4bit OTAPDLYSEL is enough.

    This is hex 0x15, which uses 5 bits.

    Tony Tang said:

    in  SDK 8.3 AM62x dts:     ti,otap-del-sel-ddr52 = <0x9>;

    in AM62x SDK9.2.:    ti,otap-del-sel-ddr52 = <0x5>;

    Since eMMC DDR mode is not supported from start, why software team keep on modify the otap delay value across SDK8.3 to SDK9.2 for AM62x, the value is much less than 15.. Is it a arbitrary change, or try to bring up DDR mode.

    I will look into it and get back to you.