Part Number: AM67A
Other Parts Discussed in Thread: BEAGLEY-AI
Hello, we currently work on creating a DDR configuration for a Micron MT53E1G32D2FW-046 IT (so quite similar to the EVM one) which should replace a Kingston B3221PM3BDGUI-U. Until now we could reuse the configuration from the BeagleY-AI which seems to come with the same Kingston DDR.
With the Micron this doesn't work reliably, so we try to create a new DDR configuration.
In fact we now have a working configuration but it seems only working when I configure the system configuration like the following:
DDR Data Bus Width (Bits) : 32
DDR Density (per x16-bit channel, per rank) (Gbit) : 8
Chip Selects / Ranks : 2
My problem now is, that I don't know why this is working. Following the datasheet the chip is a "Dual-Die, Dual-Channel, Single-Rank Package" and in my understanding I should configure the system configuration like the following:
DDR Data Bus Width (Bits) : 32
DDR Density (per x16-bit channel, per rank) (Gbit) : 16
Chip Selects / Ranks : 1
I assume that also based on the note of the Ranks field: "Although the LPDDR4 interface has a unique chip select for each channel, usage of CS0_A and CS0_B should be considered 1 rank."
However with that the system boots but when using tools like "memtest" I get reproduceable kernel panics.
I also compared the default configuration, where I assume that it matches the J722s EVM (with Micron MT53E2G32D4DE-046 AUT:C). Here it seems to align with the datasheet.
"Quad-Die, Dual-Channel, Dual-Rank Package"
DDR Data Bus Width (Bits) : 32
DDR Density (per x16-bit channel, per rank) (Gbit) : 16
Chip Selects / Ranks : 2
Can someone explain that behaviour?
When playing around with the values I also recognized that the DDRSS_PLL_FHS_CNT define changes from 3 to 5 when increasing the rank count. Might it be possible that increasing the rank count only "solves" the issue because it influences other values used during DDR init?
Best regards Martin