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c5535 LDO not powering up

Milind Shastri
Prodigy 140 points 
Hello!

My team and I are experiencing a problem with powering up a c5535. The board around the DSP has been designed to be similar to the C5535 ezDSP board with USB, I2C, and UART channels set to the datasheet recommended levels. 

Issue:
We are not able to observe DSP_LDO_OUT at its desired 1.3V level. It is at 0 V.
ANA_LDO_OUT is also at 0V.

Input connections:
int1/=10k pullup to 3.3v
int2/=10k pullup to 3.3v
reset/=3.3v

CLK_OUT=10k pulldown to gnd
CLK_SEL=10 pulldown to gnd

LDOI=3.3V (different from ezDSPs 1.8V; however when I re-wired the ezDSP w LDOI @3.3V it works just fine)
DSP_LDO_EN/=GND



I'm wondering what could cause such an issue of LDO not powering up at all. The circuit has been checked for connections and they all seem to be right. The voltage has not gone out of range and power supply has been limited to 25mA. 

Thanks,
Milind

  • 0
    TI__Genius 14965 points

    Hi,

    Could you check BG_CAP pin connected by 0.1uF to AGND?  Is power provided to VDDA_ANA?

    Regards,

    Hyun

  • 0 in reply to Hyun Kim
    Prodigy 100 points

    Hi,

    I will measure the voltage on the BG_CAP pin and report back to you.  I will also check to make sure that the cap itself is correctly placed, not shorted, etc.  IF there is no voltage on BG-CAP, what's next?

    The VDDA_ANA and VDDA_PLL are connected to ANA_LDOO. Which unfortunately does not seem to be operating. We can, with some difficulty cut a trace to isolate ANA_LDOO from the 2 loads. That would allow us to power  VDDA_ANA  and CVDD as well as DVDDIO  from a lab power supply.

    I have re-read the data sheet and it appears that if we disable the DSP_LDO, by taking LDO_EN/ high, that disables the internal POR circuits, which are AND'D with the external reset signal.

    Other suggestions?

    Mike

  • 0 in reply to Hyun Kim
    Prodigy 140 points

    Hi Hyun,

    I just got the boards back from an x-ray inspection. The board assembly does not seem to have issues.

    I checked the BG_CAP voltage and it is at 0.0V. Also as Mike pointed out, the VDDA_ANA and VDDA_PLL are connected to ANA_LDOO which are not powering up.

    We are also contemplating powering the core directly with a 1.3V power supply to see if the chip powers up as it removes the dependence on the analog core being powered on to power the band gap. However this would require some delicate messing around with the PCB.

    What could be looked at next?

    Best,

    Milind

  • 0 in reply to Milind Shastri
    TI__Genius 14965 points

    Hi,

    I reviewed your schematic and found out that your CVDDRTC connected to DSP_LDO_OUT. This is the cause of your failure.

    The CVDDRTC must always be powered. That means it should be connected not using DSP_LDO_OUT but the external power. Please refer page 53 Table 3-17 CVDDRTC signal description tms320c5535 data manual.

    And C5535eZdsp schematic shows that CVDDRTC is using external 1.3V.

    Regards,

    Hyun

  • 0 in reply to Hyun Kim
    Prodigy 140 points

    Thats right Hyun. Thank you for pointing it out!

    On powering the Cvdd_RTC with 1.3V the LDO now appears to power up. DSP_LDO_OUT=1.3V; ANA_LDO_OUT=1.3V, BG_Cap=0.7V

    Best,

    Milind

  • 0 in reply to Hyun Kim
    Prodigy 10 points

    Hi Hyun, 

    What are the demands on the external LDO that CVDDRTC needs? 1.05 - 1.3V according to specification but the specification says nothing about the maximum current that the LDO needs to be able to source? 

    Best regards 

    Anders