AM620-Q1: Information on Physical bit interleaving

Rahulsai Parthasarathy

Part Number: AM620-Q1
Other Parts Discussed in Thread: AM620

Hi Team,

Kindly let us know if AM620 sitara processor has physical bit interleaving feature on L1, L2 cache and On-chip RAM to mitigate MBU (Multi-bit upset) Single effect event.

Regards,

Rahul

7 days ago

0 PaulM 7 days ago

TI__Mastermind 31025 points

Rahul

These memories Memories support ECC, but do not have physical bit interleaving.

--Paul

0 Rahulsai Parthasarathy 1 day ago in reply to PaulM

Prodigy 30 points

Paul,

Kindly let us know on how to mitigate MBU for this processor RAM, Cache and for DDR. Do you have any Single event effect analysis document for same.

Regards,

Rahul

0 PaulM 1 day ago in reply to Rahulsai Parthasarathy

TI__Mastermind 31025 points

Rahul

I'm looping in a colleague to comment on the MBU Mitigation.

The reliability information is available by clicking the link on the Ordering and Quality table. However, I we do not published a SER report.

--Paul

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AM620-Q1: Information on Physical bit interleaving