Other Parts Discussed in Thread: TMS320C6748
The I2C documentation states that all I2C interrupts (stop condition, rx/tx, arbitration lost, etc...) are arbitrated through one interrupt. You can read sub-interrupt that triggered the interrupt from the Interrupt Status register. However, if multiple interrupts arrive the arbiter will keep the time order of events, it will re-order by priority.
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After the CPU reads I2CISR, the following events occur:
1. The source interrupt’s corresponding flag bit in I2CSTR is cleared. Exception: The AAS, ARDY,
ICRRDY, and ICXRDY bits in I2CSTR do not clear when I2CISR is read. Please refer to Table 7 for
details on how to clear these flag bits in I2CSTR.
2. The arbiter determines which of the remaining interrupt requests has the highest priority, writes the
code for that interrupt to I2CISR, and forwards the interrupt request to the CPU.
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I cannot find the priority of these interrupts in the documentation, and googling / these forums have not yielded exact results.
What are the priorities of the interrupts below (How will the arbiter order them)?
XRDYINT
RRDYINT
ARDYINT
NACKINT
ALINT
SCDINT
AASINT
Here is the I2C reference documentation:
