Hello!
I am using C6416 device. Periodically I have to download large chunks of data to FPGA. FPGA is connected to EMIFA and works in 64-bit mode. According to spru234, largest element size ESIZE is 32 bit. To use it one must align SRC/DST addresses on word boundary. However, for 64-bit peripheral 64-transfer possible, if ESIZE is 32 bit. I wonder, whether double word alignment required in such case. As per spru234 it is required for fixed mode addressing, but is it required for increment addressing? Say, if I have SRC 0x0004, doest it qualify for 64-bit transfer in increment addressing mode?
Also I wonder about element count in such case. For fixed more there is strict requirement for ELECNT to be even. But if I use increment addressing, would transfer of, say, 9 words use four 64-bit transfers and one 32-bit transfer?
Thanks in advance.