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SRIO configuration on c6474

Akhilesh Khemka
Prodigy 20 points

Hi,

I have a design issue while configuring SRIO on TI 6474 multicore DSP.

I have to use SRIO in the Direct IO mode. As per the requirement, 2 cores of the DSP would be sending data in Downlink to a common FPGA over SRIO interface. I plan to bind these 2 cores to 2 of available 4 LSUs (i.e, core 0 to LSU1 and core 1 to LSU2). 

Size of data submitted by each core to their respective LSUs is greater than 256bytes (packet size of SRIO) but less than 2700bytes. We have assigned equal priority to each LSU.
Now my query is, if both the cores submit their request to their respective LSUs simultaneously, is it guaranteed that complete data from one core would be transmitted over SRIO link before the SRIO transmits data belonging to other core. Or, SRIO peripheral can multiplex data from 2 LSUs in chunk of 256bytes.
Actually we have a requirement from FPGA, that data from one core should be completely transmitted before data from another core is sent.

Does SRIO provide any configuration to guarantee the same or I need to take care of this requirement in software.

Thanks,

Akhilesh

  • 0
    TI__Intellectual 2415 points

    Akhilesh,

    In this case, the SRIO peripheral will multiplex data from 2 LSUs in chunk of 256bytes. The SRIO does not provide any configuration to satisfy the requirement from your FPGA. Yes, you need to go ahead and take care of this in the software.


    Thanks,

    Karthik.

  • 0 in reply to Karthik Ramana Sankar
    Prodigy 20 points

    Hi Karthik,

    Many thanks for the reply.

    I was just wondering if the SRIO behavior would remain the same, assuming one of the cores (say core 0) posts request to LSU1 just an instant before another core (core 1). If core 0 posts request to LSU1 and while SRIO starts transmitting this packet (and still has outstanding packets in LSU1), SRIO receives another request on LSU2. Is it still possible that SRIO would multiplex these packets while transmitting. Or SRIO might transmit the complete packet from LSU 1 first (before transmitting packet from LSU2) given the fact that it received the request from LSU 1 before.

    Thanks,

    Akhilesh

  • 0 in reply to Akhilesh Khemka
    TI__Intellectual 2415 points

    Hi Akhilesh,

    Yes. Even in the scenario mentioned by you, the SRIO LSU HW will multiplex packets while transmitting. My suggestion for meeting your FPGA requirement is that, take an interrupt on the successful completion of the DIO transfer. Route the interrupt from LSU1(core0) to Core1 and route the interrupt from LSU2(core1) to Core0. Design the 2 LSU ISRs in such a way that we can always make sure both DIO transactions from Core0 and Core1 do not happen simultaneously. Configure the LSU interrupt condition routing registers (ICRR) for routing the LSU interrupts accordingly.

    Thanks,

    Karthik.