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EMIF interface in C5515

Anuj Aggarwal
Expert 3990 points

Hi,

One of my customers is trying to interface a 8-bit 512 KB SRAM using EMIF interface in C5515. CPU is running at 100 MHz. He is using 10ns access time for the 512K x8 SRAM.

He is facing two problems:

a) There is no signal on the EM_BA[0] line, it is always High. But it comes for 16 bit interface.

b)  Read cycle time is 60 ns with the following break-up where as the expectations are <= 50 ns:

Setup = 10 ns

Strobe = 20 ns

Hold + ??? = 30 ns

The connections have been made as per Fig 1-8 a) of the EMIF Manual.

I tried referring to our eZDSP kits or EVMs but nowhere we have used 8 bit SRAM. Is there something which is not being done correctly?

I have also attached the SRAM datasheet for your reference.

Thanks.

7558.512KX8 2V4 SRAM 61-64WV5128EDBLL.pdf

  • 0
    Prodigy 125 points

    Did you set the BYTEMODE bits of the EMIF System Control Register to 8-bit accesses?

    See Section 1.2.8 of the EMIF User's Guide (SPRUGU6A)

  • 0 in reply to Jeremy White
    TI__Expert 3990 points

    Yes, here is the register dump:

    ESCR = 0 ; // Word Mode Access for Configuration

    ECDR = 1 ; // EMIF Clock Frequency = 100 MHz

    ACS2CR1 = 0x0084 ;

    ACS2CR2 = 0x0010 ;

    AWCCR2 = 0xF000 ;

    AWCCR1 = 0x0000 ;

    ESCR = 2 ; // Byte Mode Access for RAM

    He tried using the "repeat unconditional" instruction to check if the performance improves but still he is seeing a cycle time of 60ns and BA[0] not toggling.

    Can you point out what could be wrong?

    Thanks.

  • 0 in reply to Anuj Aggarwal
    Prodigy 125 points

    The register settings look reasonable and similar to mine (I have a UART connected instead of an SRAM, but the principle is the same).

    I programmed your EMIF settings for my board and measured the BA[0] signal on an oscilloscope.  When I read from an address in that chip space, I see a signal that starts high and pulses low for about 40ns, which is consistent with your setup/strobe/hold settings for a 100MHz clock.

    I also verified that if ASIZE (in ACS2CR1) = 8-bit data bus, then BA[0] toggles, but if ASIZE = 16-bit data bus, then it does not toggle.

    Given your register settings, it's not clear why BA[0] would not toggle in 8-bit mode, unless there is a hardware problem.

    Regarding the 60ns read cycle time you are seeing, have you measured the SYSCLK frequency at the CLKOUT pin to verify it is indeed 100MHz and not 60MHz ?