Dear All,
Dear All,
With reference to the Cortex-A8 User Manual : Page Number 874
6. The subroutine handler executes code specific to the peripheral generating the interrupt by handling
the event and de-asserting the interrupt condition at the peripheral side.
; IRQ0 subroutine
IRQ0handler:
; Save working registers
STMFD SP!, {R0-R1}
; Now read-modify-write the peripheral module status register
; to de-assert the M_IRQ_0 interrupt signal
; De-Assert the peripheral interrupt
MOV R0, #0x7 ; Mask for 3 flags
LDR R1, MODULE0_STATUS_REG_ADDR ; Get the address of the module Status Register
STR R0, [R1] ; Clear the 3 flags
Can any body say me ..where i can find the defination for LDR R1, MODULE0_STATUS_REG_ADDR ; MACRO.
Thanksa nd Regard's
Hrishikesh.
