Hardware Describes:
CPU DM3730
Camera Pin connections to FPGA
D[0:11] I
PCLK I
HS I
VS I
PCLK I
HS I
VS I
CAM_WEN I
I ：means input
I ：means input
Data from Camera interface through ISP, and the CPU get data from DMA ram.
We don't need the ISP module to do any change the data from the camera interface.
Data Format: 24bit RGB, 2 clock transfer 1 pixel.
One Frame Data = 1024*600*2*12bit.
This is all problems that we have met:
* I still not very sure that if the date could be passed into DM3730 memory correctly. I have check the PDF data. And I only could sure about
that there is on 4 data types(8/10 bit RAW, 11/12 bit RAW, BT 656 8/10 bit, YUV 8/10 bit ) the Camera ISP allowed data flows.
* I tried not to use all the modules that in ISP but i can't get any data in my memory.
* I doubt that when the data type is not standard format the hardware decoder can't work. So the data I get is zero.
Our current register configurations
ISP_SYSCONFIG =0x1001
ISP_CTRL =0x40 09 c1 4c
TCTRL_CTRL =0x0
ISP_IRQ0ENABLE =0x0
CCDC_SYN_MODE =0x3 04 20
CCDC_PCR =0x0
CCDC_HORZ_INFO =0x31f
CCDC_VERT_START =0x0
CCDC_VERT_LINES =0x257
CCDC_CFG =0x8800
CCDC_HORZ_INFO =0x31f
CCDC_VERT_START =0x0
CCDC_HSIZE_OFF =0x640
CCDC_SDOFST =0x0
CCDC_SDR_ADDR =0x90d0e000
CCDC_VDINT =0x2570000
RSZ_PCR =0x4
RSZ_CNT =0x3fcff
RSZ_OUT_SIZE =0x0
RSZ_IN_START =0x0
RSZ_IN_SIZE =0x0
RSZ_SDR_OUTADD =0x0
RSZ_SDR_OUTOFF =0x0
