Hi,
To improve DSP C674x data I/O in DM814x(Da Vinci), we have to allocate ping-pong buffer in L1D SRAM and L2 SRAM.
So we do some experiment and encounter some problems.
(1) L1D SRAM and L2 SRAM
According to TMS320C674x DSP Cache User Guide(sprug82a.pdf), there should be some chip support library(CSL) commands to set the size of L1D cache and L2 cache, such as:
CACHE_L1dSetSize();
CACHE_setL2Size();
But we can't find it in our software package. Is there chip support library available for C674x?
Currently the only way for us is to modify L1D and L2 control register directly.
For instance,
#define L1DCFG *((volatile unsigned int *) (0x01840040)
#define L2CFG *((volatile unsigned int *) (0x01840000)
L1DCFG = 0x3; // Set L1D cache size to 16KBytes
L2CFG = 0x2; // Set L2D cache size to 64KBytes
(2) To test DMA we use function DAT_copy(), which is from EDMA3 LLD package (edma3_lld_02_11_04_01\examples\CSL2_DAT_DEMO).
For instance,
DAT_copy(src, dst, 16384);
DAT_wait(DAT_XFRID_WAITALL);
DMA transfer only works when both src and dst are in DDR2 memory. However, if dst is either in L1D or L2 SRAM, DMA transfer fails.
Do the function families such as DAT_copy(), DAT_fill(), DAT_copy2d() support L1D and L2 SRAM?
How do we perform DMA transfer between DDR2 memory to L1D/L2 SRAM?
(3) The design of ping-pong buffer is to grant DSP access and DMA transfer at the same time, the current data set is processed by DSP and the next data set is prepared by DMA.
Is there any bandwidth issue if L1D SRAM is accessed by DSP and DMA simultaneously? (I mean if there is address consideration for ping-pong buffer?)
Thanks.
