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AM3703 DDR routing clarification

Other Parts Discussed in Thread: AM3703

Hello,

As per the datasheet of AM3703, a balanced T routing is recommended when using two DDR chips as shown below

There is no data for maximum length allowable for B or C length. It is recommended that the length for A should me maximized and B & C should be equal.

My question is what is the acceptable level for B&C lengths compared to A length, say in terms of percentage?

Regards,

Vini

  • Hello Vini,

    That is not included in the spec to help keep the guidelines as simple as possible.  If you follow all of the guidelines all of the lengths will be withing spec.

  • Hello Jeff,

    I do not understand it. I will follow the guideline and use balanced T route for clock, address and control lines.

    But what is the accepted length for B & C sections compared to section A? Is it OK if the length of section B is equal to length of section A?

    The diagram is again shown below (I am not sure why it didn't come in last post, though I inserted it)

    Regards,

    Vini

  • Hi Vini,

    As long as you are maintaining the nominal trace length rule (NO 5) and A to B, A to C skew (NO 10) and B to C skew (NO 11) your A to B and C distances will be within spec.  It is advised that you try to maximize the A length.  If you can find a configuration that has A=B=C and it doesn't violate any of the other rules then it will be within spec.  Please remember to add the treminator distance when figuring in the rule NO 5.

  • Thanks Jeff,

    You said that  it is advised that you try to maximize the A length but isn't it better to reduce the 'A' length to the min possible, so that the impedance mismatch (Z0/2 for dual DRAM configuration) is as close as possible to the Processor to improve signal integrity?

    Regards,

    Vini

  • It is better to have the memory as close as possible.  The comment for the A length is with respect to B and C.