Hello,
I am new to DDR3 and I'm sorry that I'm not able to translate it properly,
so this question may be quite unclear.
Regarding the DDR3 Routing Guidelines.
Our 3P wants to know if it is possible to exchange DDR3 pins in their respective bus group.
They say if that is possible, they can change the bus order to avoid unwanted VIA routings.
In case of "length matching", if there is a twist in a single trace then length of all other
traces should be changed and if reordering the DDR3 pins is not allowed the layout get expanded.
Please let me know if anybody understood the idea behind and whether this kind of desing is allowed.
Regards.