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Why is C6678 MPAX Segment 2 enabled at power-up

Jonathan White
Intellectual 830 points

Document SPRUGW0B (CorePac User Guide) explains in section 7.3 that MPAX segments 0 and 1 are enabled by default.

But I have noticed that MPAX segment 2 is also enabled by default at power-up.

0x08000000   000000BF 0000001E 800000BF 8000001E 100000F6 2100000B 00000080 00000000
0x08000000   00000080 00000000 00000080 00000000 00000080 00000000 00000080 00000000
0x08000000   00000080 00000000 00000080 00000000 00000080 00000000 00000080 00000000
0x08000000   00000080 00000000 00000080 00000000 00000080 00000000 00000080 00000000
0x08000000   00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

I would like to know why, as I was planning to use MPAX segment 2 for another purpose.

This is with C6678 EVM board, Silicon Rev 1.0

  • 0
    Genius 3770 points

    Hi White,

    The segment 2 should be available after reset, only segment 0 and 1 have their own default mapping scheme.

    But  the GEL(evmc6678l.gel) will invoke a function called xmc_setup() to setup the mapping of segment 2 in order to access the DDR EMIF configuration space.

    So it's a better way to start from segment 3 if you want to make the mapping of your own.

    Allen

     

  • 0 in reply to Allen Lee
    Intellectual 830 points

    Thanks Allen. The values I see certainly match the ones in xmc_setup (which I have pasted below).

    But the odd thing is I am not explicitly using a GEL file. Perhaps one gets loaded by default when connecting using CSS? Although that seems a bit intrusive.

    I will do more experiments in different boot modes (PCIe with R1.0 silicon and IBL workaround, and PCIe with 2.0 silicon without IBL, and standalone CCS load, etc).

    void xmc_setup()
    { 
        /* mapping for ddr emif registers XMPAX*2 */
        CSL_XMC_XMPAXL    mpaxl;
        CSL_XMC_XMPAXH    mpaxh;

        /* base addr + seg size (64KB)*/ //"1B"-->"B" by xj */
        mpaxh.bAddr     = (0x2100000B >> 12);
        mpaxh.segSize   = (0x2100000B & 0x0000001F);

        /* replacement addr + perm*/
        mpaxl.rAddr     = 0x100000;
        mpaxl.sr        = 1;
        mpaxl.sw        = 1;
        mpaxl.sx        = 1;
        mpaxl.ur        = 1;
        mpaxl.uw        = 1;
        mpaxl.ux        = 1;

        /* set the xmpax for index2 */
        CSL_XMC_setXMPAXH(2, &mpaxh);
        CSL_XMC_setXMPAXL(2, &mpaxl);   
    }

  • 0
    Expert 2021 points

    I have also noticed that MPAX segment 2 is "automatically" configured at C6674 power-up when a GEL file is not used. The reason for this has not been given in this post, but I think I have found it. TI has published the source for the C6678 ROM bootloader (RBL), and the following code can be found in the chipSetEntryState function in nysh.c (applies to both RBL versions 1.0 and 2.0):

        /* Configure the MPAX to make the DDR3 configuration registers visible */
    /*   */
        i = 0x000000f6;
        DEVICE_REG_XMPAX_L(2) =  0x10000000 | i;     /* replacement addr + perm*/
        DEVICE_REG_XMPAX_H(2) =  0x2100000B;         /* base addr + seg size (64KB)*/