6678 connect to FPGA with SRIO interface

guoping Lee

Other Parts Discussed in Thread: TMS320C6678

I am interesting in communication between FPGA and DSP through SRIO interface.Does the connection between SRIO interface of DSP and GTX interface of FPGA should be AC-Couple?Is the Pullup resistance necessary? the DSP is TMS320C6678 and FPGA is xilinx vertix-5.thanks

over 13 years ago

0 Karthik Ramana Sankar over 13 years ago

TI__Intellectual 2415 points

Hi Lee,

For more information regarding interfacing with TI SERDES, please refer to Chapter 8 "Termination" of the HW design guidelines for keystone devices (http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=sprabi2a&fileType=pdf).

Thanks,

Karthik.

0 Tom Johnson 16214 over 13 years ago in reply to Karthik Ramana Sankar

TI__Mastermind 46460 points

Guoping Lee,

Yes, you will need capacitors in series with the SRIO links. The DC-bias of the Xilinx FPGA will not be the same as the DC-bias of the DSP. The SERDES RX pins are placed close to the edge oif the DSP so that if these capacitors are placed near to the DSP, then there will be no additional vias needed.

Tom

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6678 connect to FPGA with SRIO interface