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OMAP-L138 - Jitter spec on EMA_CLK?

M.A.M
Expert 8805 points

Hi,

Is there a figure available for the max jitter (cycle-cycle, period) on the EMA_CLK?

The worries come from a note on jitter of another PLL branch, so we guess it is in the same order for SYSCLK3 or DIV4.5:

(SPRUH77A–December 2011, page 142)

NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of 50 MHz +/-50 ppm.

/Magnus

  • 0
    TI__Guru* 84075 points

    Hi Magnus

    No we do not have any jitter spec for specific clock outputs. I talked to design team on this and essentially EMIF timing is based on meeting setup and hold relative to data. CLK jitter is taken into account for the spec timings. We don't have a separate spec for clock output jitter and this is not something we characterize and specify at a device level.

     Looking at the PLL specs , the clockout jitter should be around +/-2.5% of the clock period . This number/data is ONLY to give a customer an idea of what to expect, and it should not be interpreted as a guarantee or a spec'd value

    It should also be understood, that factors outside the chip/device, like noise on the IO etc, can also impact jitter and there is no control on that from the device side.

    Regards

    Mukul