C5505 - SPI chip select glitch

Todd Anderson78572

All:

Setup: C5505 running at 65 MHz, SPI clock rate 4 MHz. -- Also seen on C5515EVM board...

When running SPI_config() from chip support library, I get a glitch on chip select lines when executing the following line of code:

/* Disable the serial Data clock */

CSL_FINST(CSL_SPI_REGS->SPICCR, SPI_SPICCR_CLKEN, DISABLED);

The SPI clock is NOT active during this glitch.

Has anyone seen this problem? Because there is no clock activity, is deemed a "non-problem?"

Regards,

Todd Anderson

over 13 years ago

0 Mark M over 13 years ago

TI__Mastermind 30170 points

Hi Todd,

I see a 330ns low pulse on SPI_CS0 during the peripheral reset...

/* Value of 'Reset Counter' */ CSL_FINS(sysRegs->PSRCR, SYS_PSRCR_COUNT, 0x20); CSL_FINS(sysRegs->PRCR, SYS_PRCR_PG4_RST, CSL_SYS_PRCR_PG4_RST_RST);

I only see a ~15ns low pulse glitch when I step over... (as you described)

CSL_FINST(CSL_SPI_REGS->SPICCR, SPI_SPICCR_CLKEN, DISABLED);

but in my version of csl_spi.c this line is commented out and replaced with...

/* Disable the serial Data clock */ CSL_FSET(CSL_SPI_REGS->SPICCR, CSL_SPI_SPICCR_CLKEN_SHIFT, CSL_SPI_SPICCR_CLKEN_SHIFT, CSL_SPI_SPICCR_CLKEN_DISABLED); //CSL_FINST(CSL_SPI_REGS->SPICCR, SPI_SPICCR_CLKEN, DISABLED); CSL_FINST(CSL_SPI_REGS->SPICCR, SPI_SPICCR_RST, RELEASE);

When I step over the CSL_FSET line, the 15ns glitch is not present.

Do you have the latest CSL release? Check for this commented line in csl_spi.c and give it a try.

Regardless, the clock is not running so the SPI device should not change state even if CS glitches low for 15ns...

Hope this helps,
Mark

0 Todd Anderson78572 over 13 years ago in reply to Mark M

Guru 14640 points

Thanks Mark. Changing that line got rid of the glitch.

Regards,

Todd Anderson

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C5505 - SPI chip select glitch