Using QMSS in SYSBIOS with MSMC problem A0,A1 etc

chunlei gan

Other Parts Discussed in Thread: SYSBIOS

HI engineers,

I have a problem that using QMSS in SYSBIOS .The demo of QMSS in the dirctory

pdk_C6678_1_0_0_16\packages\ti\transport\ipc\examples\qmssIpcBenchmark used the datamemory and codememory in the L2SRAM,but

I want to use the datamemory and codememory in the MSMC because of using one executing file.

But when I use the datamem and codemem in the MSMC ,there are some problems like following:

---->

 [C66xx_0] A0=0xc136d18 A1=0x1
	[C66xx_0] A2=0x0 A3=0x201802b
	[C66xx_0] A4=0xc136d18 A5=0xfffffffb
	[C66xx_0] A6=0xc13f540 A7=0x1
	[C66xx_0] A8=0xc13ec94 A9=0x0
	[C66xx_0] A10=0xc13ec1c A11=0x1
	[C66xx_0] A12=0x2 A13=0xc13ec94
	[C66xx_0] A14=0xc148988 A15=0x0
	[C66xx_0] A16=0xc13ec4c A17=0x0
	[C66xx_0] A18=0xc13ec1c A19=0x20
	[C66xx_0] A20=0x6c A21=0x4c
	[C66xx_0] A22=0x0 A23=0x1
	[C66xx_0] A24=0x800002 A25=0x80090008
	[C66xx_0] A26=0x0 A27=0x0
	[C66xx_0] A28=0x0 A29=0x100
	[C66xx_0] A30=0xc1483dc A31=0x0

What is the problem of A0 A1 etc ? And how can I to resolve like these?

regards

over 14 years ago

0 Tom Kopriva over 14 years ago

TI__Mastermind 20480 points

Hi Chunlei,

I don't understand your question. What is the MSMC? I'll try to get your question pointed to someone who can help.

Can you provide the version of SYS/BIOS, XDCtools you are using?

0 chunlei gan over 14 years ago in reply to Tom Kopriva

Prodigy 160 points

HI ,

My sysbios version is 6.31.04.27 and XDCtools is 3.22 .My CCS version is 5.0.3.

My question is that when i use the datamemory and codememory in the L2 ,the demo runs Ok ,when i set the datamemory and codememory in the MSM (Multicore

Shared Memory which addr is 0x0c000000 of C6678),there will be the problem like these:

 A0=..,A1=..

 etc....

how can i resolve the problem of these?

regards.

0 chunlei gan over 14 years ago in reply to Tom Kopriva

Prodigy 160 points

HI TOM,

the web has some errors .

My sysbios version is 6.31.04.27 and XDCtools is 3.22 .My CCS version is 5.0.3.

 My question is that when I use the datamemory and codememory into the L2 ,the demo runs OK,

 when I set the datamemory and codememory into the MSM (Multicore

 Shared Memory which addr is 0x0c000000 of C6678),there will have problems like those.

 I couldn't understand the meaning of the A0 ,A1,A2 etc .How can I resolve the problems of A0,A1,A2,etc.

what is the A0,A1,A2 in the C6678? I don't find these.thanks

regards

chunlei

0 Karthik Ramana Sankar over 14 years ago in reply to chunlei gan

TI__Intellectual 2415 points

Hi Chunlei,

My understanding here is that, moving code from local L2 to MSMC will not be an issue. However, you should be careful while, moving data from local L2 to MSMC. In this example, we have two cores accessing data and if the data is placed in MSMC, then care should be taken in the code, to avoid race conditions while accessing the same data from the MSMC memory.

It would be very helpful, if you can give more details about what code (functions) and data structures are moved from L2SRAM to MSMC. Please, can you send me the qmssIpcBenchmark_c6678.out and qmssIpcBenchmark_c6678.map of the modified project, which is failing at your end. Please, also share the linker.cmd file which automatically gets generated. The linker.cmd file can be found at:

<CCS_INSTALL>\pdk_C6678_1_0_0_17\packages\ti\transport\ipc\examples\qmssIpcBenchmark\Debug\configPkg

I will try to reproduce this error at my end.

0 chunlei gan over 14 years ago in reply to Karthik Ramana Sankar

Prodigy 160 points

HI ,Sankar,

My purpose is that core0 triggers core1 with IPC ,and when these two cores are running , I want to core0 and core1 can communicate with QMSS .

Core0 triggering core1 with IPC in the SYSBIOS is OK ,but the codemem and the datamem must set at the MSMC ;but the demo of QMSS was set the

datamem and codemem at the L2SRAM ,there is the conflict for the IPC (in the MSMC)and QMSS(in the L2SRAM).When I set the datamem and codemem

at the MSMC ,the wrong like A0,A1... When I set the datamem and codemem at the L2, the IPC could not trigger core1.

So could you help me how can I set the IPC and the QMSS in the right space?

regards

chunlei.

0 chunlei gan over 14 years ago in reply to Karthik Ramana Sankar

Prodigy 160 points

hi Sankar,

I am sorry,three files of .out .cmd and .map could not .The web prompting "This type of file is not allowed. "

I will upload my project tomorrow.

thanks ,

regards.

chunlei

0 chunlei gan over 14 years ago in reply to chunlei gan

Prodigy 160 points

hi Sanker,0825.project.rar

this is my project.Please help me to look for the problems,thanks

regards

chunlei

0 Karthik Ramana Sankar over 13 years ago in reply to chunlei gan

TI__Intellectual 2415 points

Hi Chunlei,

I was able to reproduce your issue on my end.

The issue here is that, both core0 and core1 encounter exceptions and the values A0, A1....A31, B0, B1....B31 etc are the dump of CPU registers when the exception occured. One possible reason for this exception is that, all data sections (.bss, .neardata, .rodata, .far, .fardata) for both cores are placed at the same memory locations in MSMC (because a single .out file is loaded on both the cores). This is causing race conditions in both core0 and core1 while accessing the same data from MSMC. This issue does not occur when the data sections are placed in the L2 (using local address), as the local L2 memory is separate for both the cores, even though they use the same local L2 address.

This issue can be fixed by placing only the data sections for core0 and core1 in separate MSMC sections (like MSMC_core0 and MSMC_core1) or put only the data sections in local L2SRAM. I used the following sections without any issues:

    SECTIONS
   {
        .text: load >> MSMCSRAM
        .ti.decompress: load > MSMCSRAM
        .stack: load > L2SRAM
        GROUP: load > L2SRAM
        {
            .bss:
            .neardata:
            .rodata:
        }
        .cinit: load > MSMCSRAM
        .pinit: load >> MSMCSRAM
        .init_array: load > MSMCSRAM
        .const: load >> MSMCSRAM
        .data: load >> L2SRAM
        .fardata: load >> L2SRAM
        .switch: load >> MSMCSRAM
        .sysmem: load > MSMCSRAM
        .far: load >> L2SRAM
        .args: load > MSMCSRAM align = 0x4, fill = 0 {_argsize = 0x0; }
        .cio: load >> L2SRAM
        .ti.handler_table: load > MSMCSRAM
        .vecs: load >> MSMCSRAM
        .xdc.meta: load >> MSMCSRAM
        .qmss: load >> MSMCSRAM
        .cppi: load >> MSMCSRAM
        .desc: load >> MSMCSRAM
        .msgQ_ptrs: load >> L2SRAM
        .platform_lib: load >> L2SRAM
        xdc.meta: load >> MSMCSRAM, type = COPY

   }

Please, let me know if this fixes the issue at your end.

0 chunlei gan over 13 years ago in reply to Karthik Ramana Sankar

Prodigy 160 points

hi ,Sankar

I was following your SECTION in the link.cmd file in the project.

But when I set the c6678 platform of datamem and codemem to the MSMCSRAM section (tools->RTSC tools->Platform->Edit/view)the issues were

also happened .

what the difference of operation between us? How did you operate the project?

Could you give me you right project ? I was dead tired of this project. :(

regards

chunlei

0 Karthik Ramana Sankar over 13 years ago in reply to chunlei gan

TI__Intellectual 2415 points

Hi Chunlei,

Add the following lines in your bench_qmss.cfg file (source):

Program.sectMap[".text"] = new Program.SectionSpec();
Program.sectMap[".text"] = "MSMCSRAM";

Program.sectMap[".ti.decompress"] = new Program.SectionSpec();
Program.sectMap[".ti.decompress"] = "MSMCSRAM";

Program.sectMap[".bss"] = new Program.SectionSpec();
Program.sectMap[".bss"] = "L2SRAM";

Program.sectMap[".neardata"] = new Program.SectionSpec();
Program.sectMap[".neardata"] = "L2SRAM";

Program.sectMap[".rodata"] = new Program.SectionSpec();
Program.sectMap[".rodata"] = "L2SRAM";

Program.sectMap[".cinit"] = new Program.SectionSpec();
Program.sectMap[".cinit"] = "MSMCSRAM";

Program.sectMap[".pinit"] = new Program.SectionSpec();
Program.sectMap[".pinit"] = "MSMCSRAM";

Program.sectMap[".init_array"] = new Program.SectionSpec();
Program.sectMap[".init_array"] = "MSMCSRAM";

Program.sectMap[".const"] = new Program.SectionSpec();
Program.sectMap[".const"] = "MSMCSRAM";

Program.sectMap[".data"] = new Program.SectionSpec();
Program.sectMap[".data"] = "L2SRAM";

Program.sectMap[".fardata"] = new Program.SectionSpec();
Program.sectMap[".fardata"] = "L2SRAM";

Program.sectMap[".switch"] = new Program.SectionSpec();
Program.sectMap[".switch"] = "MSMCSRAM";

Program.sectMap[".sysmem"] = new Program.SectionSpec();
Program.sectMap[".sysmem"] = "MSMCSRAM";

Program.sectMap[".far"] = new Program.SectionSpec();
Program.sectMap[".far"] = "L2SRAM";

Program.sectMap[".args"] = new Program.SectionSpec();
Program.sectMap[".args"] = "MSMCSRAM";

Program.sectMap[".cio"] = new Program.SectionSpec();
Program.sectMap[".cio"] = "L2SRAM";

Program.sectMap[".ti.handler_table"] = new Program.SectionSpec();
Program.sectMap[".ti.handler_table"] = "MSMCSRAM";

Program.sectMap[".vecs"] = new Program.SectionSpec();
Program.sectMap[".vecs"] = "MSMCSRAM";

Program.sectMap[".xdc.meta"] = new Program.SectionSpec();
Program.sectMap[".xdc.meta"] = "MSMCSRAM";

I am also attaching my bench_qmss.cfg file for your reference. For more details about "Placing Sections into Memory Segments", please refer to chapter 6 of the BIOS6 users guide:

<CCS_INSTALL>\bios_6_32_05_54\docs

1070.bench_qmss.zip

0 chunlei gan over 13 years ago in reply to Karthik Ramana Sankar

Prodigy 160 points

hi ,

Thank you for your help ,the issues were not happened.And the core1 can run normally. :)

But when I set all of the 8 cores to run in the project,there will be some errors and the core1 to core7 were not run .

What should I pay attention when I set all 8 cores running ?Did I leave out something to set?

I will test more to resolve the problems.

regards

chunlei

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Using QMSS in SYSBIOS with MSMC problem A0,A1 etc