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Is C6745 EMIFB.EMB_SDCKE signal level based on JEDEC requirement durling SDRAM initialization?

j-breeze
Mastermind 7560 points

Hi Champ,

I'd like to ask you a question mentioned in this subject.

According to C6745 Datasheet (sprs377d, page-32) and TRM (spruh91a, page-195), EMIFB.EMB_SDCKE terminal is in 3-stated and the signal level is "H" due to intenal pullup resistor after power up.

But then, Micron and EtornTech SDRAM require "CKE = L" in the power up and initialization.  

So, is C6745 EMB_SDCKE base on JEDEC requirement? Can I use these SDRAMs with C6745?

Thank you very much in advance.

Best regards,
j-breeze

  • 0
    Mastermind 7560 points

    Hi Champ,

    Any information about JEDEC requirement related to CKE signal level in the power up and initialization sequence would be appreciated.
    Could you please let me know whether C6745 EMIFB is compliant JEDEC SDRAM standard or not?

    Thanks in advance for your cooperation.

    Best regards,
    j-breeze

  • 0 in reply to j-breeze
    TI__Guru 68920 points

    Hi j-breeze,

    Maybe you could point us to the JEDEC spec in question here, so we can look at the details.

    Regarding CKE,  I found this FAQ on Micron's site, which talks to a concern about a possible invalid value being written to the SDRAM's mode register.

    (see http://www.micron.com/products/dram/sdram.html)

    The 6745 EMIFB will cause an initialization sequence explictily again when you configure it.

    Please see the note on page 862 of SPRUH92A.   When you write to SDCFG this will cause a new SDRAM initialization sequence.

    So, you're not dependent on any power on configuration to set the SDRAM mode - the SDRAM will be explicitly initialized when the EMIF is programmed.

    Best Regards,

    Anthony