EMIF 16 configuration in TMS320C6678

Johannes

Hi,

I'm trying to use the EMIF 16 interface in 6678 and I have some questions that I couldn't figure out a solution:

1 - Is there any example code for C6678? The examples I found are only for older DSPs.

2 - The only way to set EMIFA[23:0] and EMIFD[15:0] is writing directly to the corresponding CE memory space?

3 - How do I set the control bits (EMIFCE, EMIFRnW...) in CCS 5.1, which header should I include? How do I set them, directly (EMIFCE = 1, for example) or using a pointer to a memory position as in the case when I want do set EMIFA and EMIFD? I think that EMIFOE and EMIFWE are set automatically when I configure the Async registers, but EMIRFRnW and EMIFCE?

4 - What's the memory position where the config registers are stored? According to the datasheet it's from 0x20C00000 to 0x20C000FF, but if I set them using the struct defined in cslr_emif16.h, simulate the code (using Functional or Cycle Approximation simulators) and use the disassembly tool there's nothing written on those positions. Is it a problem with the simulator or I shouldn't use those structs defined in the header file?

5 - In the header file cslr_emif16.h (...\Texas Instruments\pdk_C6678_1_0_0_17\packages\ti\csl), where the registers related to EMIF16 are defined, there are some registers like IOCR that aren't described either in the 6678 datasheet or in the KeyStone Architecture External Memory Interface (EMIF16) - SPRUGZ3A document, where do I find what those registers do?

Thanks in advance for any help.

over 12 years ago

0 Aditya over 12 years ago

TI__Expert 6815 points

1. Are there examples for specific endpoints that you are looking for? example, ASRAM/NAND etc. For which DSP do you have examples that you are looking at?

2. The procedure is different for different memories. What you say applies to memories like ASRAM that use the address lines for addressing and data lines for data accesses - you just write desired data to the desired address and the EMIF16 controller takes care of the data transfer. Note that memories like NAND behave a little differently in that they use the data bus for multiplexed data/address accesses. You need to program the ALE and CLE addresses depending on which address pin is used for those functions. In short, the user software needs to take care of read/write command and data sequencing per the NAND device datasheet.

3. The control signals (EMIFCE, EMIFRnW, EMIFWE, EMIFOE etc) are toggled by the EMIF16 controller depending on the access in progress. The user does not and cannot toggle these directly in software.

4. You are correct. The config space ranges from 0x20C00000 -> 0x20C000FF. Can you check in PSC if you have powered up the EMIF16 module? If it is powered down you won't be able to access its registers.

5. I believe IOCR, IOSR, IODFTEXECNT, IODFTGBLCTRL,IODFTTLAMISR,IODFTTLDMISR & IODFTTLDCMISR are all reserved fields in this device and should not be touched by the user. I do not know how they got through to external documentation but they are reserved in the users guide. If there is any discrepancy, please assume that the users guide is correct and let us know if you have any questions. Thanks a lot for bringing this to our attention.

0 Johannes over 12 years ago in reply to Aditya

Mastermind 6240 points

Hi Aditya,

Thanks a lot for your answer.

1 - In the Application Report SPRA542A (TMS320C6000 EMIF to External Asynchronous SRAM Interface) there some configuration examples for C6211 and C6711, it was used <emif.h> that contained functions to set the registers. As I understand, now there isn't this header anymore, we should use the CSL headers.

However, for emif16 we only have the cslr_emif16.h, we don't have the Aux headers, like we do for gpio, emif4h..., and the functions used to set the registers are defined in those Aux files , that's why I asked for an example code. And by now I couldn't set the emif registers yet.

2 - You're right, I always talking about the ASRAM memories, sorry for not mentioning it.

3 - So the EMIF16 controller identifies if I'm doing a read (load the value from a memory position and stores in a variable) or a write (puts a value in a memory position) and take care of the configuration bits?

4 - I checked the PSC, the modules were really disabled. I enabled them, set the NextState and the StateTransition and checked the PSC registers, the domains are enabled, but the module clocks are disabled (bit 12 MCKOUT in Module Status Register (MDSTATy) is disabled). Any idea why the module clock is disabled? I've tried to work with the resets enable (local isolation) but it had no effect. I think that maybe the EMIF registers are not storing the values in memory because the EMIF module clock is disabled.

Thanks again for the help.

0 Aditya over 12 years ago in reply to Johannes

TI__Expert 6815 points

Joh,

1) Yes you should use CSL headers. We do not support the CSL functional layer APIs for EMIF16 (the ones found in the peripheral Aux files). However, you can use the CSL register layer (RL) macros along with the field definitions provided in cslr_emif16.h to configure your registers as desired.

For example, if you want to configure CS5 is 8-bit mode, you can use the following RL macro:

CSL_Emif16Regs EMIF16_REGS;

CSL_FINS(EMIF16_REGS.A4CR, EMIF16_A4CR_ASIZE , 0);

3) You are right. The controller logic will toggle the relevant control signals.

4) You need to also enable the module LPSC (or module clock). You seem to be familiar with the PSC terminology which is good. I just want to ask you if you followed the steps laid out in "Section 2.3.2 Module State Transitions" in the PSC users guide (SPRUGV4B).

0 Johannes over 12 years ago in reply to Aditya

Mastermind 6240 points

Aditya,

Yes, I folowed the steps in Section 2.3.2, I also tried to enable the power domain and the module together (section 2.3.3) and I keep getting the corresponding MCKOUT = 0, instead of 1. In section 2.3.3 we have :

"4. Set PTCMD.GO[X] 0x1 to initiate the state transition(s). The PSC will turn on the logic / memory for that particular domain, starts the module clock, then de-asserts the module reset."

We can check if these actions have been done in the MDSTAT register, the state is Enable (0x3), but the Module clock is off (MCKOUT is 0) and the local reset is asserted (LRST is 0). But the transition is completed PTSTAT.GOSTAT[X] = 0. So it's not setting the clock and the local reset.

One more question, what power domain should I enable for EMIF16 or it is always ON and I only have to enable the module?

Thanks

0 Aditya over 12 years ago in reply to Johannes

TI__Expert 6815 points

Joh, EMIF16 is on Always-ON domain. You would just need to enable the LPSC. Just to clarify, are you using the C6678 simulator provided in CCS or the EVM? I am not sure how EMIF16 behaves in the simulator since I have not tried it, but if you can give me details (CCS version, simulator release etc) I can try to reproduce the issue here and get back to you.

0 Johannes over 12 years ago in reply to Aditya

Mastermind 6240 points

Hi Aditya,

I'm using the the C6678 Device Functional Simulator (I don't have the EVM yet, but it's arriving soon =) ). The version of CCS and simulator is 5.1.

I also fear that the simulator can't simulate EMIF16 and PSC completely.

Thanks.

0 Aditya over 12 years ago in reply to Johannes

TI__Expert 6815 points

Joh, the simulator will not simulate the EMIF16 as in real life since it is fundamentally an external memory. You should still be able to write to EMIF16 config space and all four data spaces as well via CCS memory window and via test code loaded in CPU. When you receive your EVM you will be able to experiment with the interface and the PSC controller on the device.

0 Johannes over 12 years ago in reply to Aditya

Mastermind 6240 points

Ok Aditya,

Thanks for your answers

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

Processors

Processors forum

EMIF 16 configuration in TMS320C6678