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Question on GPMC interface with C6A8168 processor.

Dinesh Potluru
Prodigy 30 points

Hi

From the SPRS680B, it is given C6Integra has 6 Chipselects upto 256MB per chip select pin
so cumulatively GPMC has address space of 1536MB.

i) Can I connect 1 GB external device(NOR) to the GPMC bus, I think it is not a valid configuration because
each chipselect supports 256MB of address space. Am I correct?

ii) In the same manual(SPRS280b) section 2.9.1 L3 memory map gives only 512MB of address space for GPMC.
Can I use 6 devices using GPMC bus each supporting 256MB of address space?

Thanks in advance

Dinesh

  • 0
    Intellectual 470 points
    1- I don't see how you can get more than 512MB since this is all the address space the GPMC is allocated. You could use a single 512MB NOR flash, but you would likely have to work the glue that switches the high order address line and the chip select for the part yourself. So you might have CS0 be the low 256MB and CS1 be the high 256MB. Then you could or these together for your parts CS and use the CS1 as the high order bit. You should check this, but it is a thought. 2- I believe the answer to this is no. There are six so that you can have several smaller devices. One other point: the lower ~2MB of GPMC memory is obscured by ROM. If you map a part that is 256MB to 0x0000_0000 then you will not be able to see approximately that size of the memory. Also, if you enable XIP NOR boot, the processor expects to boot from 0x0800_0000 which means that this might wind up in the middle of your flash part if you map a 256MB part at 0x0000_0000. My advice is to think about why you want to be in NOR and what you think it is going to buy you and consider NAND. I base this on several things, including the improving life of NAND with SLC and large densities (if you get a 8GB SLC NAND, it's lifetime will probably rival your 1GB NOR), support for NAND in the part, the increasing use of NAND over NOR in other products, etc.
  • 0 in reply to Stephen Hicks
    TI__Guru*** 125430 points

    You can't occupy more memory than has been allocated in the memory map (i.e. 512 MB for this device).  You could have 4 chip selects of 128MB each or you could have 8 chip selects of 64 MB each or some other combination.

    Based on the number of address pins it looks like you could only address 128MB without any glue logic.  Due to the address pin limitation I think you'd need some glue logic similar to what's shown here:

    http://processors.wiki.ti.com/index.php/Connecting_NOR_Flash_to_OMAP-L138#Hardware_Connection_for_64Mx16_device