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DMA to, from GPMC bus

MATT GESSNER
Expert 1435 points

Hi,

I've attached a code snippet I'm using to set up a DMA transfer between an FPGA on the GPMC bus and SDRAM.

What's happening is that DMA4_CSR(0).BLOCK is never being set.  On the GPMC bus, however, we see two sets of writes to the chip: the for-loop that initializes the FPGA RAM area to zeros, and then the DMA activity.  We see 64 bytes being transferred, but only DMA4_CSR.LAST and DMA4_CSR.HALF are being set; the loop always times out.

With the exception of the DATA_TYPE field in DMA4_CSDP, this code is identical to code that I wrote to test copying from SRAM to SDRAM.

So what could be going wrong here that I never see the end of block, even though all of the data is being transferred?

__writel is nothing more than

*(volatile uint32_t *) addr = val

Thanks,

Matt Gessner

  • 0
    Expert 1435 points

    OK, it turned out that the board we were using fails, but another board we have (which I was just able to load FPGA code into today) works great, as well as another board we tested.

    So now my question is, given the code sequence I posted, is there something I could be doing that would result in a more efficient transfer?

    And is the BLOCK bit in the CSR the only bit I care about which indicates the end of the transfer?

    Thanks,

    Matt Gessner