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How to config DVO2(vout0) of DM8168 to output BT656 signal?

ge zhiming
Intellectual 470 points

At my board one sd encoder such as adv7179 connect to dvo2, we want to use svo2 to output 8bit embsync signal.

But the HDVPSS driver not support output PAL/NTSC mode by HDVENC DVO2 port, I added some config params, but can not output normal PAL/NTSC signal to ADV7179, The TV cannot detect any signal.

vpllCfg.outputVenc  = VPS_SYSTEM_VPLL_OUTPUT_VENC_A;

vpllCfg.outputClk   = 27000；

clkSrc.venc         = VPS_DC_VENC_DVO2;
clkSrc.clkSrc       = VPS_DC_CLKSRC_VENCA;

dcOutputInfo.dataFormat     = FVID2_DF_YUV422SP_UV;
dcOutputInfo.dvoFmt = VPS_DC_DVOFMT_SINGLECHAN;

I print all registers of vout0, mode=ntsc:

offset             val

    0 44003058
    4 003f0275
    8 1ea500bb
    c 1f9901c2
   10 1fd71e67
   14 004001c2
   18 00200200
   1c 1b6c0c77
   20 1c0c0c30
   24 1c0c0c30
   28 8420d35a
   2c 3e11c015
   30 3e2d8074
   34 00000105
   38 00038338
   3c 3e2d008a
   40 00016000
   44 000f011c
   48 030040f0
   4c 0300110d
   50 0010e10a
   54 3e2d0082
   58 00016001
   5c 000f011c
   60 030010f0
   64 030040fa

  • 0
    Intellectual 470 points

    Follow is added for ntsc mode

    HdVenc_StdModeInfo HdVencStdModeInfo[] = {

        {{FVID2_STD_480I, 720, 480, FVID2_SF_INTERLACED, 0, 30,
            19,  57,  62, 4, 15, 3}, VPSHAL_HDVENC_DMODE_480I, 4, 4},


  • 0 in reply to ge zhiming
    Intellectual 470 points

    I modify ntsc params to:

        {{FVID2_STD_NTSC,720*2, 480, FVID2_SF_INTERLACED, 0, 30,
            38, 114, 124, 4, 15, 3}, VPSHAL_HDVENC_DMODE_480I, 4, 4},

    As you see I double all the horizontal params the TV can detect video and display.

    But the picture on the TV only show left partion at horizontal, the right partion is black, and the color of left picture not right, seem white and black color is ok, but other color seem missing blue.

  • 0 in reply to ge zhiming
    Intellectual 470 points

    the registers for ntsc is:

     [m3vpss ]  DVO2   VENC: --------------Register info--------------
     [m3vpss ]  DVO2   VENC: Reg[0x4810a000] = 0x44003058
     [m3vpss ]  DVO2   VENC: Reg[0x4810a004] = 0x003f0275
     [m3vpss ]  DVO2   VENC: Reg[0x4810a008] = 0x1ea500bb
     [m3vpss ]  DVO2   VENC: Reg[0x4810a00c] = 0x1f9901c2
     [m3vpss ]  DVO2   VENC: Reg[0x4810a010] = 0x1fd71e67
     [m3vpss ]  DVO2   VENC: Reg[0x4810a014] = 0x004001c2
     [m3vpss ]  DVO2   VENC: Reg[0x4810a018] = 0x00200200
     [m3vpss ]  DVO2   VENC: Reg[0x4810a01c] = 0x1b6c0c77
     [m3vpss ]  DVO2   VENC: Reg[0x4810a020] = 0x1c0c0c30
     [m3vpss ]  DVO2   VENC: Reg[0x4810a024] = 0x1c0c0c30
     [m3vpss ]  DVO2   VENC: Reg[0x4810a028] = 0x8420d6b4
     [m3vpss ]  DVO2   VENC: Reg[0x4810a02c] = 0x7c11c015
     [m3vpss ]  DVO2   VENC: Reg[0x4810a030] = 0x7c5a80eb
     [m3vpss ]  DVO2   VENC: Reg[0x4810a034] = 0x00000105
     [m3vpss ]  DVO2   VENC: Reg[0x4810a038] = 0x00038338
     [m3vpss ]  DVO2   VENC: Reg[0x4810a03c] = 0x7c5a0114
     [m3vpss ]  DVO2   VENC: Reg[0x4810a040] = 0x00016000
     [m3vpss ]  DVO2   VENC: Reg[0x4810a044] = 0x000f011c
     [m3vpss ]  DVO2   VENC: Reg[0x4810a048] = 0x030040f0
     [m3vpss ]  DVO2   VENC: Reg[0x4810a04c] = 0x0300110d
     [m3vpss ]  DVO2   VENC: Reg[0x4810a050] = 0x0010e10a
     [m3vpss ]  DVO2   VENC: Reg[0x4810a054] = 0x7c5a010c
     [m3vpss ]  DVO2   VENC: Reg[0x4810a058] = 0x00016001
     [m3vpss ]  DVO2   VENC: Reg[0x4810a05c] = 0x000f011c
     [m3vpss ]  DVO2   VENC: Reg[0x4810a060] = 0x030010f0
     [m3vpss ]  DVO2   VENC: Reg[0x4810a064] = 0x030040fa
     [m3vpss ]  DVO2   VENC: Reg[0x4810a068] = 0x00000000
     [m3vpss ]  DVO2   VENC: Reg[0x4810a06c] = 0x00000000
     [m3vpss ]  DVO2   VENC: Reg[0x4810a070] = 0x00000000

  • 0 in reply to ge zhiming
    Intellectual 745 points

    Hi

    I am also facing the same issue. Same video on half of the screen. Can anyone from TI help us out?

    Regards

    Ayusman