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Moving text section in MSMC or DDR3

Pankaj Kumar
Intellectual 300 points

Hi,

We are using Keystone family of Multicore DSP. We wanted to use most of L2 SRAM as data memory because cache coherancy is handled in hardware and one does not need to maintain it using software.Therefore, I am  thinking to move text section in MSMC or DDR3.  I am able to see some performance loss but that will be distributed across in comparison to writeback/invalidate where it is concentrated at the instance. 

Before moving ahead, I need to understand the following

1. Are there any forseeable issues with moving text section in shared memory. Can I mark part of shared memory as read only by all the cores and peripherals?

2. I am planning to use L1P cache as 32K. So will text section always be cached irrespective of shared memory being cacahed or not. It will be of help if you could point me to some documentation for this

3. Is there some better mechanism of achieving this?

Regards,

Pankaj

  • 0
    Genius 4330 points

    Hi Pankaj

    1、You can use the MPU. Please refer to the document sprugw5.pdf

    2、The MSMC code will always be cached in the L1P cache.   The section 4.3.7.4 L1 Interaction of document 《sprugw0b.pdf》 said :The MAR registers have no effect on L1P. If L1P is enabled, it will always cache  program fetches regardless of MAR configuration.