I am using omap-l137 evm to set up the ping pong buffer.
I can get audio samples with McASP1 and replay it which sounds ok.
Then I add a ping pong buffering with EDMA3. I can see that EDMA does transfer since it generates interrupts which I can count.
But the data is not seen in the buffer. The buffer does not seem to be changing. The buffer content does not look like filled with audio samples.
I placed the buffers on L2RAM. The PaRAM#2 and PaRAM#66 is set up as follows.
Any idea on what it is wrong.
#define NUM_OF_BYTES_PER_WORD 4 // ACNT = 32Bits
#define NUM_OF_WORD_PER_BUFFER 128 // BCNT = 128 samples= processing frame size
#define NUM_OF_BUFFER 1 // CCNT
void init_PaRAM_McASP_Rcv_event2 (void)
{
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_EVENT2].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC & ITC Chaining; Set TCC)
edma3ccRegs->PARAMSET[EDMA_EVENT2].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT2);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_EVENT2].SRC = (Uint32) &(mcaspRegs-> RBUF0);
edma3ccRegs->PARAMSET[EDMA_EVENT2].DST = (Uint32) &RcvBuffers[0];
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_EVENT2].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_WORD) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2*NUM_OF_WORD_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_EVENT2].CCNT = NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_EVENT2].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, NUM_OF_BYTES_PER_WORD);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_EVENT2].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_EVENT2].LINK_BCNTRLD =
//CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)0xFFFF) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_EVENT66] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2*NUM_OF_WORD_PER_BUFFER);
//************** Parameter Set 66 *******************//
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_EVENT66].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC & ITC Chaining; Set TCC)
edma3ccRegs->PARAMSET[EDMA_EVENT66].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT2);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_EVENT66].SRC = (Uint32) &(mcaspRegs-> RBUF0);
edma3ccRegs->PARAMSET[EDMA_EVENT66].DST = (Uint32) &RcvBuffers[2*NUM_OF_WORD_PER_BUFFER];
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_EVENT66].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_WORD) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2*NUM_OF_WORD_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_EVENT66].CCNT = NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_EVENT66].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, NUM_OF_BYTES_PER_WORD);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_EVENT66].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_EVENT66].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_EVENT2] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2*NUM_OF_WORD_PER_BUFFER);
}