HDVPSS Queries

Hi

Answers inline, I am not getting all answers correctly, but I will try to answer as far as i can

Swapnil Kanani said:

Does TI have any solution which can multiplex 2 1080p stream and generate BT.1120 output?

TI has a solution which can capture 2 1080P60 or it can generate 2 1080P60 independent outputs through display. I am not sure what multiplexing means here.

Swapnil Kanani said:

Can user set output level of Video DAC of DM816x device? e.g: In default state Video DAC of Netra gives 0.5Vpp. Is it possible to configure output to 1Vpp through register setting?

This is not possible. But you can use filters for it.

Swapnil Kanani said:

Can HD-DAC in DM816x run 2x over sampled? If we have video format whose base pixel clock is in the range of 40-43MHz, is it possible to output video at 2x over sample?

DAC also runs at pixel clock. Its not possible to ouptut at 2X the pixel clock, while pixel clock. But Venc itself can run at 2X pixel clock whereby Y and UV are time multiplexed with double rate pixel clock.

Swapnil Kanani said:

Analog video outputs of DM814x and DM816x have different output level? Is it possible to have identical circuit at the output of video DACs of both the device.

There is no HDDAC in DM814x.

Swapnil Kanani said:

Is it possible to operate DM814x SD DAC output at 54MHz oversampled?

Venc can be ran in 54MHz, but its not possible to run DAC only at 54MHz and Pixel clock at 27MHz. Any specific requirement for this.

Regards,

Hardik Shah

Additional input for questions 1

Like TVP5158, which can multiplex four D1 channel. I am looking for a decoder which can multiplex 2 1080P inputs.

Our end product requirements are

1) 4 channel D1 input

2) one 1080p30 input

3) one 875p30 input

We are planning to use TVP5158 for multiplexing 4- D1 channel. The encoded video stream will be given to one input port of Centaurus. To accommodate 20 bit 4:2:2 encoded video stream corresponding to 1080p30 and 16 bit 4:2:2 encoded stream corresponding to 875p30, we are planning to use Netra.

We would like to go for single SOC solution instead of two. Please suggest.

Swapnil

Hi,

I am not aware of any decoder that support 1080P30 with multiplexed input. But since VIP port can support pixel clock till 165MHz you can have FPGA to convert 16-bit BT1120 input to VIP to 8bit Y and YUV multiplexed input BT656 to VIP. This should be done for 1080P30 and 875P30. Many customer have done this. There are forum threads also on this. If you are able to achieve this you can use total 4 VIP ports(2 instance) each configured as 8 bit. So 1 port can be used for 4D1, other two can be used for 1080P30 and 875P30. Still you will be left with one extra port.

In short 1080P30 and 875P30 will be mostly BT1120 standard. If you can convert it to BT656 using some FPGA or may be some chip is already available you can achieve your usecase using DM8168 only.

Regards,

Hardik Shah

Hi Hardik,

It would be great if you can redirect me to the discussion forum which shows the usage of FPGA for conversion from BT.1120 to BT.656.

Regards,

Swapnil

Hi,

It was asked on forum i guess. But I dont have clear idea on who asked or who is the customer who is doing that.

Regards,

Hardik Shah

TVP7002 datasheet explicitly mentions that it supports 1080p30 but 875p30 is not mentioned in the datasheet.Is there a way to configure TVP7002 to support 875p30 analog input.

We would love to have single chip for our solution. As of now we are using ADV7181C(analog device decoder) for 875p30 decoding application.

Best Regards,

Swapnil

Hi,

I will forward your query to TVP7002 team here and get the answer.

Regards,

Hardik Shah

Any update on above thread?

Swapnil

Hi,

 I have forwarded query to TVP7002 design engineer here. It seems he is on leave. Please expect answer by this week end or early next week.

Regards,

Hardik Shah

Hi,

Discrete sync input with TVP7002 for 875p30 should be possible. But embedded sync is not possible.  So if you are planning to give through VGA input than it should be possible.

Regards,

Hardik shah