This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

How to run SRIO_LoopbackDioIsrexampleproject?

I am trying to run the SRIO_LoopbackDioIsrexampleproject that is included with pdk_C6670_1_0_0_17. Unfortunately the readme file in the example directory isn't very helpful.

Am I supposed to run it on just one core (i.e. core 0) or on multiple cores?

Or should it be run on two cores that are connected via sRIO (i.e. on different chips)?

Should I be setting the TEST_MULTICORE define variable?

thanks

Greg

  • Hi Greg,

    The SRIO_LoopbackDioIsrexampleproject that is included with pdk_C6670_1_0_0_17, should be run only one core (Core0). The SRIO HW is configured in internal digital loopback mode. By default the TEST_MULTICORE is not set in the project build settings. There is no need to set the TEST_MULTICORE in the project build settings. Let me know, if you need further support to get this example working on your end.

  • When I run on one core it gets into an infinite loop at device_srio_loopback.c line 207 because CSL_BootCfgGetSRIOSERDESStatus is not showing that the SERDES PLL is not locked.

    Is this because I am running the example on a CommAgility 2C6670 board instead of a TI EVM?

    thanks

    Greg

  • Hi Greg,

    Yes. The SRIO SERDES settings in SRIO_LoopbackDioIsrexampleproject are specific to C6670 EVM. The SERDES settings need to be modified according to CommAgility 2C6670 board. What is the value of the SRIOSGMII clk on the CommAgility 2C6670 board? The SRIOSGMII clk on the C6670 EVM is 250 MHz. Once you know the exact value of the SRIOSGMII clk used on your board, refer to Table 2-7 "Frequency Range versus MPY Value" in the SPRUGW1A to configure the SERDES_PLLCFG register accordingly.

  • I adjusted the SerDes MPY setting as above and the example is now working.

    thanks

    Greg