How to configure MSMC SRAM?

Hi,

As far as I know he MCSM cannot be configured as an L2 or L3 cache, but it is by default an L2 RAM (not a cache), cachable in L1.

It can be configured as an L3 RAM, that is cachable in L2 and L1 cache, by means of the PAX and MAR registers.

Since the MAR registers that control the "cachability" of the MCSM memory (0x0C000000/+4M) are not writable, first you have to remap the MCSC to another address and then enable or disable the cache for that address as desired (while it will be is always accessible from address 0x0C000000 as L2 RAM).

Hi Alberto,

Thanks for your response. Your understanding about MSMC memory in C6678 is correct. For more details, please refer to section 4.3.7 Cacheability Controls in the C66x CorePAC users guide:

http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=sprugw0b&fileType=pdf

More details about MAR registers can be found in section 4.4.4 Memory Attribute Registers (MARn) of the C66x CorePAC users guide.

Hi Alberto,

Thanks for the reply. Could you please clarify more..

What does it mean by saying that MCSM is by default an L2 RAM. Does all the data accessed from external memory pass through MCSM?

Can DDR3 data be cached in mcsm or L2/L1?

Even if it is cached;  coherency must be maintained through software because cache coherency is maintained by hardware  only between L1 and L2 of same core and between L1 D and corresponding segment in shared memory.

If so, inorder to reduce memory read/write latency of DDR3, IS DMA paging from DDR3 TO MCSM  a better option?

I need to process large size of data, hence shared memory is not sufficient. How can I reduce the memory latency caused due to DDR3 access.

Regards,

Sohal

Hi,

As saied, the MCSM is not a cache, so access to external memory never  pass through the MCSM

MCSM is an L2 memory, cachable at L1,  that is it is accessed throught the L1 cache. Its access normaly don't pass throught the External Memory Controller

External memory is L3 memory, that can be configured non-cachable (the default) and accessed directly, or configured cachable and accessed throught the L1 and L2 cache.

The MCSM can be configured all or in part as L3 memory, that is accessed throught the External Memory Controller, and became non-cachabe or cachable both on L2 and L1 (assuming L2SRAM is configured as cache). Since when configured as L3 is is accessed throught the Extenral memory Controller, this kind of access is slower then the L2 mode, but can benefit of the L2 cache.

The MCSM is also connected to the DDR, only to be usable as a DMA source/destination from/to the DDR.

HIMO, the DMA is good option mainly if you can something with the CPU diuring the Transfer. You can process a set of data while the DMA is trasfering the next set of data (double buffer). In this way you can work in parrarel but you have to pay for the contention on the MCSM.

In any case you have to deal with the coherency.

I think the best choice depenent on your specific applicaiton requirement and it is hard to give the right suggestion.

For instance, for my applications I configure the L2SRAM as cache (512K) and then I let the cache controller do the dirty work. For my particular application, working on the DDR (with the aid of the L2 cache) is faster then using the MCSM.