DM8107/DM814x details

Feroz,

None of these interfaces need to have their rise/fall times specified. They are specified in terms of the layout and loading characteristics.

For #1) do you mean rise/fall TIME or rise/fall DELAY? Again, the rise/fall times are governed by the trace loading characteristics. Delay times are governed by trace lengths and impedance matching requirements. If the rules in the datasheet are followed then all constraints for the DDR will be met.

For #2) do you mean for the interface from the DM to the PHY or from the PHY to the connector? I assume you mean from the PHY to the connector since you mention differential? This information should come from the PHY datasheet. For SD I didn't think the interface was differential?

For #3) USB guidelines are referenced on page 367 of the DM8148 datasheet.

BR,

Steve

Hi Steve,

    1) I need the Rise/Fall TIME & Rise/Fall DELAY both.

    2) I need the information for following signals for DM to PHY interface:

       1)TX Data

       2)RX Data

       3)TX CLK

       4)RX CLK.

       Thank you.

Regards,

Feroz

Feroz,

I believe all this is in the datasheet under section 8.6.2

For the data signals the rise and fall times are not specified explicitly but the guaranteed valid high/low (90%) are given in table 8-17 and other tables in this section for various modes.

BR,

Steve

Hi Feroz,

   I need the Impedance only for Ethernet(Ethernet to PHY interface) & SD card.

   I need  Rise/fall TIME & Rise/fall DELAY for DDR3 & USB2.0 interface.

  Consider TMS320DM8107 processor (TMS320DM8148 as reference) as main processor.

Thank you.

Regards,

Vishal Dhanani.