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Details about HW issue with CPSW driver on AM335x

Damjan Marion
Prodigy 140 points

Hi,

One of the commits[1] related to CPSW linux driver are mentioning that there is HW issue with CPSW interrupts and linux driver is using timers to workaround this. However details about this issue are not described in public errata.

Can somebody provide a bit more details about this issue?

Does it affect operation of device when pacing is disabled and CPSW RX and TX interrupts are used?

My observation so far is that interrupts stop working when I reset CPDMA even with pacing disabled.

Thanks,

Damjan

[1] http://arago-project.org/git/projects/linux-am33x.git?p=projects/linux-am33x.git;a=commit;h=8c32c4f2798e652d51920bfdd9d5ad32be68f565

  • 0
    TI__Guru 62855 points

    The Ethernet Media Access Controller/Switch subsystem (CPSW SS) C0_TX_PEND and C0_RX_PEND interrupt outputs provide a single transmit interrupt that combines transmit channel interrupts TXPEND[7:0] and a single receive interrupt that combines receive channel interrupts RXPEND[7:0].

    The TXPEND[0] and RXPEND[0] interrupt outputs were connected to the ARM Cortex-A8 Interrupt controller (INTC) rather than the C0_TX_PEND and C0_RX_PEND interrupt outputs.  This only allows channel 0 to interrupt the ARM Cortex-A8. 

    The C0_TX_PEND and C0_RX_PEND interrupt outputs are the only interrupt outputs that support interrupt pacing.

    If transmit channel interrupts 1-7, receive channel interrupts 1-7, or interrupt pacing is required the C0_TX_PEND and C0_RX_PEND interrupts can be routed to the ARM Cortex-A8 Interrupt controller (INTC) through two of the AM335x timers.

    A description of this problem and a workaround will be released in the next version of the AM335x Silicon Errata.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 140 points

    Thanks Paul for this detailed explanation.

    Seems that my issue is not related to this, as I'm using only channel 0.

    Can you please check if my transmit sequence is ok:

    1. Disable TX & RX interrupt receive for core 0 (set C0_TX_EN and C0_RX_EN to 0)
    2. Reset CPSW_SS and wait for reset to complete
    3. Reset and init SL port 1
    4. Reset CPDMA and wait for reset to complete
    5. Set all HDP and CP registers to 0
    6. clear all int masks [TR]X_INTMASK_CLEAR to 0xFFFFFFFF
    7. enable TX & RX DMA (write 1 to [TR]X_CONTROL)
    8. enable interrupts for TX and RX channel 0 (write 1 to [TR]X_INTMASK_SET)
    9. Enable interrupt receive for core 0 (set C0_TX_EN and C0_RX_EN to 0xFF)
    10. Write values 0,1 and 2 to CPDMA_EOI_VECTOR
    11. Write pointer to TX_HDP0

    After this sequence my packet is sent and can be captured on network but interrupt is not triggered.
    If I skip step 4 (CPDMA reset) and leave CPDMA in state left by U-boot, i start receiving interrupt storm, which is strange but it (hopefully) proves that my interrupt handling routine is fine.

    Your help is really appreciated.

    Regards,

    Damjan