Dear E2E:
Thank you for your help.
Can you please help me to find the following information about McASP on OMAP-L138?
1. I am reading "General Initialization Procedure" for McASP in the document SPRUH77, page1070-1072.
"Take the respective frame sync generators out of reset by setting the RFRST bit for receiver and/or the XFRST bit for transmitter."
2. In the GLBLCTL register description I am reading "XFRST=1 Transmit frame sync is active. "When released from reset , the transmit frame sync generator begins counting serial clocks and generating frame sync as programmed", page 1117.
3. How long (how many clocks) it takes for AFSX to start after releasing from reset - setting XFRST=1?
4. In my case AFSX will be generating every 256 clocks.
5. How many clocks I need to wait from the setting XFRST=1 to the first AFSX to be active on the output? I think - this should be in the device documentation.
6. For example - McBSP section provides these data for McBSP "The internal frame sync signal FSG is generated on a CLKG active edghe after 7 to 8 CLKG clocks", page1204.
7. Can you please provide the same information for McASP?
Thank you for your help,
Boris Ruvinsky
