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c6701 mcbsp bit error rate

si cheng
Expert 2685 points
hello, I am using c6701, I have 2 c6701, connect with mcbsp, c6701 works in 80mhz, mcbsp in 40mhz, I send data from one dsp to the other with dma, I found that there is some bits error during transfering! I want to know if there is bit error rate with mcbsp,if yes, how can I reduce the bit error rate! Thanks!
  • 0
    TI__Guru* 84110 points

    Si Cheng,

    Why do you operate the C6701 so slow at 80MHz? Do you generate the McBSP clock from the internal divider or do you use an external clock for the McBSP clock?

    There should be no bit errors, if all signals are clean from noise and the McBSP clock does not exceed CPUCLK/2.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Expert 2685 points
    Hello, I use the internal clock, how can I make sure all signal are clean from noise?
  • 0 in reply to si cheng
    TI__Guru* 84110 points

    It is good that you use the internal clock.

    You must look at the signals with test equipment such as an oscilliscope.

    There should be no bit error rate. Noise or bad timing are the only things that could cause problems, that I can think of.

    Noise:

    • examine the signals with a high-impedance oscilloscope
    • try adding series resistors or parallel capacitors to signals to remove noise

    Timing:

    • setup a test where you send the same data and see if you get errors
    • look at when the data transitions - which edge of the clock is it close to?
    • look at the McBSP registers to see if there are settings to change the clock edge when signals are sampled or generated

    Regards,
    RandyP

  • 0 in reply to RandyP
    Expert 2685 points

    hello,

    Can I read data from FPGA to sram with DMA channle 3 and read data from sram to mcbsp with DMA channle 2  at the same time ?  FPGA and sram are both in the CE space of c6701.

  • 0 in reply to si cheng
    TI__Guru* 84110 points

    Si Cheng,

    Because you marked this thread as Answered, other experts will be less likely to look here to see if you still need an answer. Please post this new question as a new thread in this same forum. Use another helpful title and include whatever information someone would need to know to help you. Since I have not used this part, I will not know this level of detail for certain.

    Did you figure out your problem that led to the original question for this thread? Since you marked it as Answered, I assume you did. If you would, please reply back to this thread with your solution. That will help future readers.

    My opinion on your new question is that, yes, you can do both transfers at the same time. Of course, there is only one external bus so  only one transaction can occur at any instant in time, but both transfers can be prepared and ready to run at the same time. There will be sharing of the EMIF bus. The FPGA and sram will use different CE spaces on the same EMIF bus; each will use a different CEn pin to select that device.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Expert 2685 points

    RandyP,

    My project start DMA channel 2 to transfer data from SRAM to MCBSP, and  don't  wait  it to transfer over, and at the same time I start DMA channel3  to transfer data from FPGA to SRAM, then there are bit errors, But if I wait DMA channel2 to transfer over, then start DMA channel3 to transfer, there is no bit error ! So I wonder if the EMIF bus conflict when both DMA channel2 and channel3 access the EMIF bus at the same time!

    thanks!

  • 0 in reply to si cheng
    TI__Guru* 84110 points

    Please explain "bit errors" and please explain the relationship of the addresses in SRAM used by the two channels.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Expert 2685 points

    hello,

     I think the problem is that  the data from FPGA  maybe cover the data in SRAM,  which lead to the mcbsp bit error, Because the addresses in SRAM used by the two channels is the same!

    thanks!