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Bus Contention for Data bus containing FPGA,DSP,Boot Flash and SBSRAM

Apratim Gupta
Prodigy 10 points
Other Parts Discussed in Thread: TMS320C6416T

My design contains Altera Cyclone II EP3C40F780, DSP of Texas Instruments TMS320C6416T, Boot Flash S29AL008J70TFI010 and and SBSRAM CY7C1470V33. which share a common data and address bus.The boot flash control signals are mapped to DSP only.The control signals of SBSRAM are mapped to FPGA. Out of 6 SBSRAMS, 4 are connected only to FPGA , one is connected to EMIF-A of DSP as well as to FPGA and another is connected to EMIF-B and  FPGA along with Boot Flash. All 4 SBSRAMS connected to FPGA and one connected to EMIF-A is working but the one connected with EMIFB is not working.  All bus control signals for both EMIFA and EMIFB are mapped to FPGA.

We are accessing all SBSRAMS now from FPGA and not from DSP. Sometimes we are able to read/write SBSRAM after power on but if we again cycle power then the EMIFB data bus remains always at HIGH logic and we are not able to read/write SBSRAM. When we probe on the address and control signals they are showing appropriate levels. Also we have not mapped BARDY,BHOLD and BHOLDA to FPGA . Does this make any difference? 

Please we need your help immediately to solve this problem. I have attached block diagram of my system below.

  • 0
    TI__Guru* 84110 points

    Apratim Gupta,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages. Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    Are you using the term "mapped" here to mean the same as "connected"? Or is everything connected together and only logical mapping is used to differentiate between physical connections? Your last statement about BARDY, BHOLD, and BHOLDA not being mapped to FPGA implies the same as a physical connection.

    The EMIFA and EMIFB buses are considered to be mastered by the C6416T. In other words, it owns those buses and will always drive the address and control lines. The exception to this is when you use the bus arbitration handshaking with the A/BHOLD and A/BHOLDA signals. If you do not use these, and you have another bus master, like the FPGA, driving signals on the bus then you will definitely have contention.

    There was no block diagram attached, but it may not be required if this addresses your question. But I would be surprised if this would be as simple as that, since you seemed to have done this correctly on the EMIFA and pointed directly to the EMIFB arbitration signals. And you have conflicting statements about "all bus control signals" but not "BARDY, BHOLD, and BHOLDA" being mapped to FPGA. Why is this confusing to me? Is it already confusing to you?

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.