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How Inter-Processor Interrput works?

Haifei Wu
Prodigy 245 points


In the document "INTC for KeyStone Devices UG", it says that when set the IPCG of IPCGRx, the corex's interrupt works.(Am i right ?). In this document, it also introduces IPCGR and INCAR (registers), SRCS and SRCC(bits). I don't know if i want to use Inter-Processor Interrupt, what pre-work and post-work should be done. Can anybody give detail information? Thank you!

  • 0
    TI__Genius 12065 points

    Haifei,

    IPC is used for interrupt communication between core to core within DSP and can also be used to communicate with external host.

    You can find some more information in the IPC section of CSL document as the follows file:

    \pdk_C6678_1_0_0_17\packages\ti\csl\docs\csldocs.chm

    You can see how those registers are being affected in the descriptions of each function.

    The usage of IPC interrupt is similar as the other interrupt generation. We have to enable CorePac INTC to accept the interrupt first and clear pending status after triggering.

    I also attached one simple example that Core0 and Core1 generate IPC interrupts to each other. You can load the same output file to both of the cores and execute the two cores simultaneously (need to make sure the CorePac INTC has been setup completely in two cores before they trigger the interrupts, you can add more delay in the source code ). 

    Hope those information helps.

    0143.IPC_Example.zip

    Sincerely,

    Steven

  • 0 in reply to Steven Ji
    Prodigy 20 points

    Hello Steven,

    I have tried to run the example you've provided without success.

    The problem is that the interrupts are never fired, which means it halts on the first while loop in the main-function. 

    I'm running on a C6616 device, but the event id seems to be correct from what I could find in the documentation. 

    Any idea what I could be missing?

    Regards

    Sebastian

  • 0 in reply to Sebastian Jegeras
    TI__Mastermind 18226 points

    Hi Sebastian,

    please check this post.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/187011.aspx

    I also attached a project that triggers an IPC from core 0 to core 1. There's synchronization in the code that makes sure everything is set up properly before the IPC interrupt is being triggered. You can load the same .out file to core 0 and 1 ...

    This was targeted for the C6678 but should work for C6670 as well ...

    Kind regards,

    one and zero

  • 0 in reply to one and zero
    Prodigy 20 points

    one and zero,

    That example worked, thank you.

    The part that was missing in the example in this thread was that the bootcfg wasn't unlocked, when I added that to the first example, that too worked as expected.

    Regards,

    Sebastian